Datasheet > UPD30550AF2-800-NN1

UPD30550AF2-800-NN1

更新时间： 2024-10-01 21:22:43

品牌	Logo	应用领域
瑞萨 - RENESAS		光电二极管
页数	文件大小	规格书
4页	361K
描述
UPD30550AF2-800-NN1

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技术参数
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UPD30550AF2-800-NN1 技术参数

生命周期：	Obsolete	Reach Compliance Code：	compliant
风险等级：	5.84	Base Number Matches：	1

UPD30550AF2-800-NN1 数据手册

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VR5500A

64-Bit MIPS^®RISC

Microprocessor

VR Series

Description

The VR5500A^™processor extends the high-performance line of NEC’s VR Series™ RISC

microprocessors. Designed as a successor to the VR5000™ and VR5432™ microprocessors,

the V^R5500A implements the 64-bit MIPS^®IV instruction set and delivers up to 1600 MIPS at

800 MHz, one of the highest MIPS-per-MHz ratios in the industry. The VR5500A's out-of-order

execution and other features offer substantial performance improvement with minimal

product redesign in current MIPS applications and compelling reasons to switch from other

architectures.

Specifications

•

High-speed operating frequency

– 1600 MIPS Dhrystone at 800 MHz

– 1200 MIPS Dhrystone at 600 MHz

0.13 mm process technology

64-bit system bus (133 MHz) with 32-bit option

Enhanced MIPS IV instruction set

1.5-volt core operation; 3.3-volt I/O operation

272-pin BGA

Full industrial -40˚C to +85˚C operating temperature range

– 800 MIPS Dhrystone at 400 MHz

– 600 MIPS Dhrystone at 300 MHz

•

Applications

•

Digital consumer products

Network storage products

Network routers and switches

Internet appliances

Color imaging products

Block Diagram

Clock

Control

Data/Address

Phase Lock

System

Loop

Interface

Unit

Write Transaction

Buffer

JTAG

I-Cache

32 KB

D-Cache

32 KB

Two-way

Coprocessor 0

48 Dual-Entry

Translation Lookaside

Buffer

Data Cache

Control Unit

Instruction Fetch Unit

N-Wire/

N-Trace

Refill

Buffer

Store

Buffer

Branch

History

Table

Return

Address

Stack

Instruction

Management

Queue

Execution Unit

Control Unit

File

Instruction Control Unit

Instruction

Commit

Reservation

Station

12 3 4

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