Datasheet > UPD30550

UPD30550

更新时间： 2024-11-21 03:56:59

品牌	Logo	应用领域
日电电子 - NEC		微处理器
页数	文件大小	规格书
27页	949K
描述
VR5500⑩ 64-/32-BIT MICROPROCESSOR

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UPD30550 数据手册

DATA SHEET

PRELIMINADRAYTAPRSOHDEUECTT INFORMATION

MOS INTEGRATED CIRCUIT

µPD30550

VR5500^TM

64-/32-BIT MICROPROCESSOR

DESCRIPTION

The µPD30550 (VR5500) is a member of the VR Series

of RISC (Reduced Instruction Set Computer)

microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by

MIPS

The VR5500 allows selection of a 64-bit or 32-bit bus width for the system interface, and can operate using

protocols compatible with the V^R5000 Series^TMand VR5432^TM

Detailed function descriptions are provided in the • V^R5500 User’s Manual (U16044E)

user’s manual. Be sure to read the manual before designing.

FEATURES

• MIPS 64-bit RISC architecture

• High-speed operation processing

• Two-way superscaler super pipeline

• 300 MHz product: 603 MIPS

400 MHz product: 804 MIPS

• High-speed translation lookaside buffer (TLB)

(48 entries)

• 64-/32-bit address/data multiplexed bus

• Bus width selectable during reset

• Bus protocol compatibility with existing products

retained

• Maximum operating frequency

• 300 MHz product: Internal 300 MHz, external 133

MHz

• Address space

400 MHz product: Internal 400 MHz, external 133

MHz

• Physical: 36 bits (64-bit bus selected)

32 bits (32-bit bus selected)

• External/internal multiplication factor selectable from

×2 to ×5.5 by increments of .5

• Virtual:

40 bits (in 64-bit mode)

31 bits (in 32-bit mode)

• Conforms to MIPS I, II, III, IV and MIPS64 instruction

sets. Instruction set extensions supported include

product-sum operation instruction, rotate instruction,

mode.

• On-chip floating-point unit (FPU)

• Supports sum-of-products instructions

• On-chip primary cache memory

(instruction/data: 32 KB each)

• 2-way set associative

• Hardware debug functions supported are N-Wire and

JTAG.

• Supports line lock feature

• Supply voltage

Core block:

1.5 V ±5% (300 MHz product)

1.6 to 1.7 V (400 MHz product)

3.3 V ±5%, 2.5 V ±5%

I/O block:

The information contained in this document is being issued in advance of the production cycle for the

device. The parameters for the device may change before final production or NEC Corporation, at its own

discretion, may withdraw the device prior to its production.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

2002

Document No. U15700EJ1V0DS01 (2nd edition)

Date Published September 2002 N CP(K)

Printed in USA

2001

12 3 4 5 6 7...27

中文翻译

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与UPD30550相关器件

型号	品牌	获取价格	描述	数据表
UPD30550A	ETC	获取价格	UPD30550A Data Sheet \| Data Sheet[04/2003]
UPD30550AF2-300-NN1	NEC	获取价格	RISC Microprocessor, 64-Bit, 300MHz, MOS, PBGA272, 29 X 29 MM, PLASTIC, BGA-272
UPD30550AF2-300-NN1-A	NEC	获取价格	RISC Microprocessor, 64-Bit, 300MHz, MOS, PBGA272, 29 X 29 MM, LEAD FREE, CAVITY DOWN, PLA
UPD30550AF2-400-NN1	NEC	获取价格	RISC Microprocessor, 64-Bit, 400MHz, MOS, PBGA272, 29 X 29 MM, PLASTIC, BGA-272
UPD30550AF2-400-NN1-A	NEC	获取价格	RISC Microprocessor, 64-Bit, 400MHz, MOS, PBGA272, 29 X 29 MM, LEAD FREE, CAVITY DOWN, PLA
UPD30550AF2-400-NN1-A	RENESAS	获取价格	UPD30550AF2-400-NN1-A
UPD30550AF2-600-NN1	RENESAS	获取价格	暂无描述
UPD30550AF2-800-NN1	RENESAS	获取价格	UPD30550AF2-800-NN1
UPD30550AGD-300-WML	NEC	获取价格	RISC Microprocessor, 64-Bit, 300MHz, MOS, PQFP208, 28 X 28 MM, FINE PITCH, PLASTIC, QFP-20
UPD30550AGD-300-WML-A	RENESAS	获取价格	64-BIT, 300MHz, RISC PROCESSOR, PQFP208, 28 X 28 MM, LEAD FREE, FINE PITCH, PLASTIC, QFP-2

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