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UPA1453H-AZ PDF预览

UPA1453H-AZ

更新时间: 2024-11-24 21:12:07
品牌 Logo 应用领域
瑞萨 - RENESAS 开关晶体管
页数 文件大小 规格书
6页 54K
描述
5A, 60V, 4 CHANNEL, PNP, Si, POWER TRANSISTOR

UPA1453H-AZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:IN-LINE, R-PSIP-T10Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8541.29.00.95
Factory Lead Time:1 week风险等级:5.42
最大集电极电流 (IC):5 A集电极-发射极最大电压:60 V
配置:2 BANKS, COMMON EMITTER, 2 ELEMENTS最小直流电流增益 (hFE):50
JESD-30 代码:R-PSIP-T10元件数量:4
端子数量:10封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):260极性/信道类型:PNP
认证状态:Not Qualified表面贴装:NO
端子形式:THROUGH-HOLE端子位置:SINGLE
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

UPA1453H-AZ 数据手册

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DATA SHEET  
SILICON TRANSISTOR ARRAY  
µPA1453  
PNP SILICON POWER TRANSISTOR ARRAY  
HIGH SPEED SWITCHING USE  
INDUSTRIAL USE  
DESCRIPTION  
PACKAGE DIMENSION  
(in m illim eters)  
The µPA1453 is PNP silicon epitaxial Power Transistor  
Array that built in 4 circuits designed for driving solenoid,  
relay, lam p and so on.  
26.8 MAX.  
4.0  
FEATURES  
Easy m ount by 0.1 inch of term inal interval.  
High hFE. Low VCE(sat).  
hFE = 100 to 400 (at IC = –2 A)  
VCE(sat) = –0.3 V MAX. (at IC = –2 A)  
1.4  
0.5 ±0.1  
2.54  
1.4 0.6 ±0.1  
ORDERING INFORMATION  
Part Num ber  
Package  
Quality Grade  
Standard  
1 2 3 4 5 6 7 8 9 10  
µPA1453H  
10 Pin SIP  
CONNECTION DIAGRAM  
Please refer to "Quality grade on NEC Sem iconductor Devices"  
(Docum ent num ber IEI-1209) published by NEC Corporation to  
know the specification of quality grade on the devices and its  
recom m ended applications.  
3
5
7
9
2
1
4
6
8
ABSOLUTE MAXIMUM RATINGS (Ta = 25 ˚C)  
10  
Collector to Base Voltage  
Collector to Em itter Voltage  
Em itter to Base Voltage  
Collector Current (DC)  
Collector Current (pulse)  
Base Current (DC)  
VCBO  
VCEO  
VEBO  
IC(DC)  
–60  
–60  
–7  
V
V
PIN No.  
V
2, 4, 6, 8: Base (B)  
3, 5, 7, 9: Collector (C)  
1, 10 : Emitter (E)  
–5  
A/unit  
A/unit  
A/unit  
W
IC(pulse)* –10  
IB(DC)  
PT1**  
PT2***  
Tj  
–1.0  
3.5  
28  
Total Power Dissipation  
Total Power Dissipation  
J unction Tem perature  
Storage Tem perature  
W
150  
˚C  
Tstg –55 to +150 ˚C  
* PW 300 µs, Duty Cycle 10 %  
** 4 Circuits, Ta = 25 ˚C  
*** 4 Circuits, Tc = 25 ˚C  
The inform ation in this docum ent is subject to change w ithout notice.  
Document No. IC-3519  
(O. D. No. IC-6339)  
Date Published September 1994  
Printed in Japan  
P
1994  
©

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