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UPA1520BH PDF预览

UPA1520BH

更新时间: 2024-11-15 22:41:43
品牌 Logo 应用领域
日电电子 - NEC 晶体晶体管开关脉冲
页数 文件大小 规格书
8页 82K
描述
N-CHANNEL POWER MOS FET ARRAY SWITCHING USE

UPA1520BH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:IN-LINE, R-PSIP-T10针数:10
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8541.29.00.95风险等级:5.38
配置:2 BANKS, COMMON SOURCE, 2 ELEMENTS WITH BUILT-IN DIODE最小漏源击穿电压:30 V
最大漏极电流 (ID):2 A最大漏源导通电阻:0.25 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PSIP-T10
JESD-609代码:e0元件数量:4
端子数量:10工作模式:ENHANCEMENT MODE
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
极性/信道类型:N-CHANNEL最大脉冲漏极电流 (IDM):8 A
认证状态:Not Qualified表面贴装:NO
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子位置:SINGLE处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

UPA1520BH 数据手册

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DATA SHEET  
Compound Field Effect Power Transistor  
µPA1520B  
N-CHANNEL POWER MOS FET ARRAY  
SWITCHING USE  
DESCRIPTION  
The µPA1520B is N-channel Power MOS FET Array that  
built in 4 circuits designed for solenoid, motor and lamp  
driver.  
PACKAGE DIMENSIONS  
in millimeters  
4.0  
26.8 MAX.  
FEATURES  
• 4 V driving is possible  
• Large Current and Low On-state Resistance  
ID (DC) = ±2.0 A  
RDS (on) 1 0.17 MAX. (VGS = 10 V, ID = 1 A)  
RDS (on) 1 0.25 MAX. (VGS = 4 V, ID = 1 A)  
• Low Input Capacitance Ciss = 220 pF TYP.  
1.4  
0.5±0.1  
2.54  
1.4 0.6±0.1  
1 2 3 4 5 6 7 8 910  
ORDERING INFORMATION  
Type Number  
Package  
CONNECTION DIAGRAM  
µPA1520BH  
10 Pin SIP  
3
5
7
9
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)  
2
1
8
4
6
Note 1  
Drain to Source Voltage VDSS  
30  
±20  
±2.0  
±8.0  
28  
V
V
Note 2  
Gate to Source Voltage  
Drain Current (DC)  
VGSS  
10  
ID(DC)  
A/unit  
A/unit  
W
Note 3  
Drain Current (pulse)  
Total Power Dissipation  
Total Power Dissipation  
Channel Temperature  
Storage Temperature  
ID(pulse)  
ELECTRODE CONNECTION  
2, 4, 6, 8 : Gate  
Note 4  
PT1  
Note 5  
3, 5, 7, 9 : Drain  
PT2  
3.5  
W
1, 10  
: Source  
TCH  
Tstg  
150  
°C  
–55 to +150 °C  
Notes 1. VGS = 0  
2. VDS = 0  
4. 4 circuits, TC = 25 °C  
3. PW 10 µs, Duty Cycle 1 %  
3. 4 circuits, TA = 25 °C  
The diode connected between the gate and source of the transistor serves as a protector against ESD. When  
this device is actually used, an additional protection circuit is externally required if a voltage exceeding the rated  
voltage may be applied to this device.  
Document No. G10598EJ2V0DS00 (2nd edition)  
Date Published December 1995 P  
Printed in Japan  
1995  
©

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