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UPA1523BH-AZ PDF预览

UPA1523BH-AZ

更新时间: 2024-10-14 20:27:55
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
8页 75K
描述
2A, 60V, 1.3ohm, 4 CHANNEL, P-CHANNEL, Si, POWER, MOSFET, FULL PACK, SIP-10

UPA1523BH-AZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:FLANGE MOUNT, R-PSFM-T10针数:10
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8541.29.00.95风险等级:5.37
雪崩能效等级(Eas):0.4 mJ配置:2 BANKS, COMMON SOURCE, 2 ELEMENTS WITH BUILT-IN DIODE
最小漏源击穿电压:60 V最大漏极电流 (Abs) (ID):2 A
最大漏极电流 (ID):2 A最大漏源导通电阻:1.3 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PSFM-T10
元件数量:4端子数量:10
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FLANGE MOUNT峰值回流温度(摄氏度):260
极性/信道类型:P-CHANNEL最大功率耗散 (Abs):28 W
最大脉冲漏极电流 (IDM):8 A认证状态:Not Qualified
子类别:Other Transistors表面贴装:NO
端子形式:THROUGH-HOLE端子位置:SINGLE
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

UPA1523BH-AZ 数据手册

 浏览型号UPA1523BH-AZ的Datasheet PDF文件第2页浏览型号UPA1523BH-AZ的Datasheet PDF文件第3页浏览型号UPA1523BH-AZ的Datasheet PDF文件第4页浏览型号UPA1523BH-AZ的Datasheet PDF文件第5页浏览型号UPA1523BH-AZ的Datasheet PDF文件第6页浏览型号UPA1523BH-AZ的Datasheet PDF文件第7页 
DATA SHEET  
COMPOUND FIELD EFFECT POWER TRANSISTOR  
µPA1523B  
P-CHANNEL POWER MOS FET ARRAY  
SWITCHING  
INDUSTRIAL USE  
DESCRIPTION  
The µPA1523B is P-channel Power MOS FET Array that built  
PACKAGE DIMENSIONS  
in millimeters  
in 4 circuits designed for solenoid, motor and lamp driver.  
4.0  
26.8 MAX.  
FEATURES  
Full Mold Package with 4 Circuits  
–4 V driving is possible  
Low On-state Resistance  
RDS(on)1 = 0.8 MAX. (@VGS = –10 V, ID = –1 A)  
RDS(on)2 = 1.3 MAX. (@VGS = –4 V, ID = –1 A)  
Low Input Capacitance Ciss = 190 pF TYP.  
1.4  
0.5 ± 0.1  
2.54  
1.4 0.6 ± 0.1  
1 2 3 4 5 6 7 8 910  
ORDERING INFORMATION  
CONNECTION DIAGRAM  
Type Number  
Package  
3
5
7
9
µPA1523BH  
10 Pin SIP  
2
1
4
6
8
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)  
10  
Drain to Source Voltage (VGS = 0)  
Gate to Source Voltage (VDS = 0)  
Drain Current (DC)  
VDSS  
–60  
V
V
±
VGSS(AC)  
ID(DC)  
20  
ELECTRODE CONNECTION  
2, 4, 6, 8: Gate  
3, 5, 7, 9: Drain  
±
2.0  
A/unit  
A/unit  
W
±
Drain Current (pulse)  
ID(pulse) *1  
PT1 *2  
PT2 *3  
TCH  
8.0  
1, 10  
: Source  
Total Power Dissipation  
Total Power Dissipation  
Channel Temperature  
28  
3.5  
150  
W
˚C  
Storage Temperature  
Tstg  
–55 to + 150 ˚C  
Single Avalanche Current  
Single Avalanche Energy  
IAS *4  
EAS *4  
–2.0  
0.4  
A
mJ  
*1 PW 10 µs, Duty Cycle 1%  
*3 4 Circuits, TA = 25 ˚C  
*2 4 Circuits, TC = 25 ˚C  
*4 Starting TCH = 25 ˚C, VDD = –30 V, VGS = –20 V 0, RG = 25 ,  
L = 100 µH  
Build-in Gate Diodes are for protection from static electricity in handing.  
In case high voltage over VGSS is applied, please append gate protection circuits.  
The information in this document is subject to change without notice.  
Document No. G11331EJ1V0DS00  
Date Published May 1996 P  
Printed in Japan  
1996  
©

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