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UPA1500B PDF预览

UPA1500B

更新时间: 2024-11-23 22:41:43
品牌 Logo 应用领域
日电电子 - NEC 开关
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8页 95K
描述
N-CHANNEL POWER MOS FET ARRAY SWITCHING USE

UPA1500B 数据手册

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DATA SHEET  
COMPOUND FIELD EFFECT POWER TRANSISTOR  
µPA1500B  
N-CHANNEL POWER MOS FET ARRAY  
SWITCHING USE  
DESCRIPTION  
PACKAGE DIMENSIONS  
The µPA1500B is N-channel Power MOS FET Array  
that built in 4 circuits and surge absorber designed for  
solenoid, motor and lamp driver.  
(in millimeters)  
4.2 MAX.  
31.5 MAX.  
FEATURES  
4 V driving is possible  
Large Current and Low On-state Resistance  
ID(DC) = ±3 A  
1
2 3 4 5 6 7 8 9 10 11 12  
RDS(on)1 0.18 MAX. (VGS = 10 V, ID = 2 A)  
RDS(on)2 0.24 MAX. (VGS = 4 V, ID = 2 A)  
Low Input Capacitance Ciss = 200 pF TYP.  
Surge Absorber, built in  
2.54 TYP.  
0.7±0.1  
1.4±0.1 0.5±0.1  
1.4 TYP.  
ORDERING INFORMATION  
ELECTRODE CONNECTION  
1, 5, 8, 12 GATE  
2, 4, 9, 11 DRAIN, ANODE  
Type Number  
Package  
6, 7  
SOURCE  
3, 10  
CATHODE  
µPA1500BH  
12 Pin SIP  
CONNECTION DIAGRAM  
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)  
2
3
4
Note 1  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current (DC)  
Drain Current (pulse)  
Repetitive peak Reverse Voltage VRRM  
Diode Forward Current  
Total Power Dissipation  
Total Power Dissipation  
Channel Temperature  
Storage Temperature  
Single Avalanche Current  
Single Avalanche Energy  
Notes 1. VGS = 0  
VDSS  
VGSS  
ID(DC)  
60  
±20  
±3.0  
±12  
65  
V
V
A/unit  
A/unit  
V
A/unit  
W
W
˚C  
˚C  
A
mJ  
D
5
1
D
6
Note 2  
Note 3  
ID(pulse)  
D
D2  
R
G
R
G
Note 4  
1
5
Note 4  
IF(av)  
3.0  
Z
D
Z
D
Note 5  
6
PT1  
PT2  
TCH  
Tstg  
IAS  
EAS  
28  
4.0  
150  
–55 to 150  
3.0  
Note 6  
9
10  
11  
D
7
3
D8  
Note 7  
Note 7  
D
D4  
RG  
R
G
0.9  
8
12  
2. VDS = 0  
3. PW 10 µs, Duty Cycle 1 %  
4. Rating of Surge Absorber  
5. 4 Circuits, T  
6. 4 Circuits, TA = 25 ˚C  
Z
D
Z
D
7
D
D
1
5
to D  
to D  
4
8
: Body Diode  
: Surge Absorber  
: Gate to Source Protection Diode  
C
= 25 ˚C  
Z
D
RG  
: Gate Input Resistance 330 TYP.  
7. Starting TCH = 25 ˚C, V DD = 30 V, VGS = 20 V 0,  
RG = 25 , L = 100 µH  
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this  
device is actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage  
may be applied to this device.  
Document No. G10597EJ2V0DS00 (2nd edition)  
Date Published December 1995 P  
Printed in Japan  
1995  
©

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TRANSISTOR | MOSFET | ARRAY | N-CHANNEL | 30V V(BR)DSS | 2A I(D) | SIP