Datasheet > UPA1454H

UPA1454H

更新时间： 2024-09-29 12:16:59

品牌	Logo	应用领域
日电电子 - NEC		晶体晶体管开关
页数	文件大小	规格书
6页	52K
描述
NPN SILICON POWER TRANSISTOR ARRAY LOW SPEED SWITCHING USE INDUSTRIAL USE

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中文翻译

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UPA1454H 数据手册

DATA SHEET

SILICON TRANSISTOR ARRAY

µPA1454

NPN SILICON POWER TRANSISTOR ARRAY

LOW SPEED SWITCHING USE

INDUSTRIAL USE

DESCRIPTION

PACKAGE DIMENSION

(in m illim eters)

The µPA1454 is NPN silicon epitaxial Power Transistor

Array that built in 4 circuits designed for driving solenoid,

relay, lam p and so on.

26.8 MAX.

4.0

FEATURES

•

Easy m ount by 0.1 inch of term inal interval.

High hFE. Low VCE(sat).

h^FE= 800 to 3200 (at IC = 1 A)

V^CE(sat)= 1.0 V MAX. (at IC = 3 A)

1.4

0.5 ±0.1

2.54

1.4 0.6 ±0.1

ORDERING INFORMATION

Part Num ber

Package

Quality Grade

Standard

1 2 3 4 5 6 7 8 9 10

µPA1454H

10 Pin SIP

CONNECTION DIAGRAM

Please refer to "Quality grade on NEC Sem iconductor Devices"

(Docum ent num ber IEI-1209) published by NEC Corporation to

know the specification of quality grade on the devices and its

recom m ended applications.

ABSOLUTE MAXIMUM RATINGS (Ta = 25 ˚C)

Collector to Base Voltage

Collector to Em itter Voltage

Em itter to Base Voltage

Collector Current (DC)

Collector Current (pulse)

Base Current (DC)

VCBO

V^CEO

V^EBO

100

PIN No.

2, 4, 6, 8: Base (B)

3, 5, 7, 9: Collector (C)

1, 10 : Emitter (E)

I^C(DC)

I^C(pulse)*

I^B(DC)

P^T1**

P^T2***

T^j

A/unit

1.0

3.5

Total Power Dissipation

J unction Tem perature

Storage Tem perature

150

˚C

T^stg–55 to +150 ˚C

* PW ≤ 300 µs, Duty Cycle ≤ 10 %

** 4 Circuits, T^a= 25 ˚C

*** 4 Circuits, T^c= 25 ˚C

The inform ation in this docum ent is subject to change w ithout notice.

Document No. IC-3520

Date Published September 1994

Printed in Japan

1994

12 3 4 5 6

中文翻译

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