Datasheet > TSI310A-133CE

TSI310A-133CE

更新时间： 2024-09-20 19:44:47

品牌	Logo	应用领域
艾迪悌 - IDT		时钟 PC 外围集成电路
页数	文件大小	规格书
2页	98K
描述
SBGA-304, Tray

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TSI310A-133CE 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SBGA
包装说明：	BGA-304	针数：	304
Reach Compliance Code：	not_compliant	ECCN代码：	3A001.A.3
HTS代码：	8542.31.00.01	风险等级：	5.81
其他特性：	ALSO REQUIRES 3.3V SUPPLY	地址总线宽度：	64
最大时钟频率：	133 MHz	外部数据总线宽度：	64
JESD-30 代码：	S-PBGA-B304	JESD-609代码：	e0
长度：	31 mm	湿度敏感等级：	3
端子数量：	304	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified	座面最大高度：	1.78 mm
最大供电电压：	2.7 V	最小供电电压：	2.3 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	31 mm
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, PCI	Base Number Matches：	1

TSI310A-133CE 数据手册

™

Tsi310 133-MHz PCI-X Bridge

Product Brief

allow full frequency range as required by the bus architecture. The two

bus clocks may be run synchronously or asynchronously, and a spread-

spectrum clock input is supported for either or both interfaces.

Device Overview

The IDT Tsi310 is a 64-bit PCI-X bus bridge that operates at speeds up

to 133 MHz, and supports transfer rates up to 1 GBps. The PCI-X

protocol is backward compatible with the PCI 2.2 bus standard ensuring

that legacy PCI-based systems are portable to the faster PCI-X environ-

ment.

Memory Buffer Architecture

The Tsi310 memory buffer architecture has the following features (see

Data/Control unit in the Block Diagram):

The Tsi310 connects two electrically separate PCI-X bus domains,

allowing concurrent operations on both buses. This results in optimal

use of the buses in various system configurations, and enables hierar-

chical expansion of I/O bus structures. The device also supports config-

urations of PCI or PCI-X mode on either bus, and in any combination.

• Two 4-Kbyte burst read buffers that support up to eight

concurrent, upstream and downstream transactions

• Two 1-Kbyte posted write buffers that support up to eight

concurrent, upstream and downstream transactions

• Two 4-Byte single data phase buffers that support transaction

forwarding in either direction

In addition, the Tsi310 provides extensive buffering and prefetching

mechanisms for efficient data transfer between two buses, facilitating

multi-threaded operation and high system throughput.

Transaction Forwarding

The Tsi310 includes one data/control unit for downstream transactions

and one for upstream transactions. Each of these identical units

contains separate buffers for burst read, posted write, and single data

phase operations. Also included in these blocks are write queues, queue

compare logic, address decoding upstream for forwarding, control logic,

and other control functions. The clocking and reset control unit manages

these common device functions.

Block Diagram

Primary

Clock PLL

Secondary

Clock PLL

Data/Control Unit

PCI-X

Interface

PCI-X

Interface

Burst Read Posted Write Single Data

Buffer

1 Kbyte

Phase Buffer

4 Bytes

4 Kbytes

The device has I/O and Memory Base Address registers and Prefetch-

able Memory Base Address registers for downstream forwarding, as

well as inverse decoding for upstream forwarding, VGA-compatible

addressing, and palette snooping for upstream transactions. The Tsi310

uses a flat addressing model and supports 64-bit addressing and dual

address cycles.

Read Queue

8 entries

PW Queue

8 entries

Bus

Slave

Bus

Master

Control

Logic

Queue

Compare

Logic

Address

Decode

Data/Control Unit

Burst Read Posted Write Single Data

Buffer

4 Kbytes

Buffer

1 Kbyte

Phase Buffer

4 Bytes

The Tsi310 responds as a medium-speed device on both PCI-X Inter-

faces, and supports fast, back-to-back transactions as a bus slave.

Bus

Master

Bus

Slave

Read Queue

8 entries

PW Queue

8 entries

Control

Logic

Queue

Compare

Logic

Address

Decode

PCI Bus Arbitration

Secondary

Bus Arbiter

The Tsi310 uses an arbiter for the secondary bus, which can be disabled

if an external arbiter is employed. When enabled, bus arbitration is

provided for the Tsi310 and up to six external masters. Each bus master

can be assigned high or low priority, or be masked off.

JTAG

Clocking & Reset

80B6000_BK001_03

PCI-X Interfaces

Opaque Addressing (Optional)

The Tsi310 has two identical PCI-X Interfaces that each handle PCI and

PCI-X transactions for its respective bus, and, depending on the type of

transaction, can act as either a bus master or a bus slave. These inter-

faces transfer data and control information flowing to and from the

blocks shown in the figure.

The Tsi310 has an optional feature that can define an opaque (unde-

coded) memory address region to facilitate applications with embedded

processors.

The Tsi310 uses the 3.3V signaling environment. It employs two phase-

locked loops (PLLs), one for the primary clock domain and one for the

secondary clock domain. The PLL for each domain is used when the

bus is operating in PCI-X mode. In PCI mode, the PLL is bypassed to

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 2

September 4, 2009

 2008 Integrated Device Technology, Inc.

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