Datasheet > TSI384-133MCEY

TSI384-133MCEY

更新时间： 2024-09-20 20:40:39

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
2页	78K
描述
Micro Peripheral IC

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TSI384-133MCEY 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.14
Base Number Matches：	1

TSI384-133MCEY 数据手册

Tsi384^™

PCI Express to PCI/X Bridge

The Tundra Semiconductor Tsi384 is a high-performance bus bridge that

connects the PCI Express (PCIe) protocol to the PCI and PCI-X bus standards.

Features

General

• PCI Express to PCI/PCI-X Forward bridge

• Transparent, Non-transparent, and

Opaque modes

• Low latency – Superior queuing and

buffering architecture maximize

throughput and minimize latency

The Tsi384’s PCIe Interface has superior performance and supports 1, 2, or 4

lanes. This enables the bridge to offer exceptional throughput performance

of up to 1 GBps.

The device’s PCI/X Interface can operate up to 133 MHz in PCI-X mode, or up

to 66 MHz in PCI mode. This interface offers designers extensive flexibility by

supporting three types of addressing modes: transparent, opaque, and

non-transparent.

• Compliant with the following

specifications:

Block Diagram

– PCI Express Base 1.1

– PCI Express PCI/PCI-X Bridge 1.0

– PCI-to-PCI Bridge Architecture 1.2

– PCI Local Bus 3.0

Clocking/

Reset

EEPROM

Controller

PCIe Interface (x4)

– PCI-X 2.0 (mode 1 only)

– PCI Bus Power Management

Interface 1.2

Posted

Writer

Buffer

Upstream

Mux Logic

Posted

PCI Express

Queue

• Configurable as 1, 2, or 4 lanes

• 512-byte maximum payload

• Advanced error reporting capability

• Supports Lane Reversal and Lane

Polarity Inversion

Interrupt

Handling

Power

Mgmt

Non-

Posted

Buffer

Non-

Posted

Queue

Posted

Queue

Writer

Buffer

Config

Registers

Error

Handling

Mux Logic

• End-to-end CRC check and generation

• Up to four outstanding memory reads

Non-

Posted

Buffer

Non-

Posted

Queue

Downstream

• ASPM L0s link state power

management

• Legacy interrupt signaling and MSI

interrupts

PCI/X

Arbiter

• Hot Plug support

PCI/X Interface

JTAG

PCI/PCI-X

80E1000_BK001_01 (Tsi384)

• 32/64-bit addressing

• 32/64-bit data

• PCI-X operation at 50, 66, 100, and

133 MHz

• PCI operation at 25, 33, 50, and

66 MHz

• Up to eight outstanding memory reads

• 4K read completion buffer

Low Power Consumption

The Tsi384 has typical power consumption of 1.3W, and incorporates

advanced power management to minimize power consumption during

operation. In addition to supporting D0, D3 hot, and D3 cold power

management modes, the device permits unused PCIe lanes to be powered

off automatically or by configuration.

• Four external PCI/X masters supported

through internal arbiter

• Support for external arbiter

• 3.3V PCI/X I/Os

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