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TPIC5203DR PDF预览

TPIC5203DR

更新时间: 2024-11-06 19:42:43
品牌 Logo 应用领域
德州仪器 - TI 开关光电二极管晶体管
页数 文件大小 规格书
13页 256K
描述
1600mA, 60V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MS-012AA, PLASTIC, SOIC-8

TPIC5203DR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, SOIC-8针数:8
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.84其他特性:ESD PROTECTED
外壳连接:ISOLATED配置:SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE
最小漏源击穿电压:60 V最大漏极电流 (ID):1.6 A
最大漏源导通电阻:0.31 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):125 pFJEDEC-95代码:MS-012AA
JESD-30 代码:R-PDSO-G8元件数量:2
端子数量:8工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:N-CHANNEL功耗环境最大值:0.962 W
认证状态:Not Qualified表面贴装:YES
端子形式:GULL WING端子位置:DUAL
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

TPIC5203DR 数据手册

 浏览型号TPIC5203DR的Datasheet PDF文件第2页浏览型号TPIC5203DR的Datasheet PDF文件第3页浏览型号TPIC5203DR的Datasheet PDF文件第4页浏览型号TPIC5203DR的Datasheet PDF文件第5页浏览型号TPIC5203DR的Datasheet PDF文件第6页浏览型号TPIC5203DR的Datasheet PDF文件第7页 
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢇ  
ꢅ ꢈꢃꢉꢊ ꢋꢋꢌꢍꢎꢂ ꢋꢏꢌ ꢁꢌꢋꢏ ꢌꢋꢀ ꢎ ꢐꢊꢀ ꢌꢈꢁꢑ ꢒ ꢀꢌ ꢃꢀ ꢌꢏ  
ꢁꢒ ꢓ ꢌꢑꢎ ꢏꢔ ꢒꢕ ꢎꢊ ꢑꢑ ꢊꢖ  
SLIS040 − SEPTEMBER 1994  
Low r  
. . . 0.26 Typ  
D PACKAGE  
(TOP VIEW)  
DS(on)  
High Voltage Output . . . 60 V  
Extended ESD Capability . . . 4000 V  
Pulsed Current . . . 8 A Per Channel  
Fast Commutation Speed  
GND  
SOURCE1  
GATE2  
DRAIN1  
GATE1  
SOURCE2  
NC  
1
2
3
4
8
7
6
5
DRAIN2  
description  
NC − No internal connection  
The TPIC5203 is a monolithic gate-protected  
power DMOS array that consists of two  
independent electrically isolated N-channel enhancement-mode DMOS transistors. Each transistor features  
integrated high-current zener diodes (Z and Z ) to prevent gate damage in the event that an overstress  
CXa  
CXb  
condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the  
human-body model of a 100-pF capacitor in series with a 1.5-kresistor.  
The TPIC5203 is offered in a standard eight-pin small-outline surface-mount (D) package and is characterized  
for operation over the case temperature range of 40°C to 125°C.  
schematic  
DRAIN1  
8
DRAIN2  
4
GATE2  
3
Q1  
Q2  
D1  
D2  
Z1  
Z2  
7
GATE1  
Z
Z
Z
C1b  
C2b  
Z
C1a  
C2a  
2
1
6
SOURCE1  
GND  
SOURCE2  
NOTE: For correct operation, no terminal pin may be taken below GND.  
ꢀꢤ  
Copyright 1994, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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