TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
Low r
. . . 0.3 Ω Typ
Pulsed Current . . . 10 A Per Channel
Fast Commutation Speed
DS(on)
High Voltage Output . . . 60 V
Extended ESD Capability . . . 4000 V
description
The TPIC5401 is a monolithic gate-protected power DMOS array that consists of four N-channel
enhancement-mode DMOS transistors, two of which are configured with a common source. Each transistor
features integrated high-current zener diodes (Z
overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using
and Z
) to prevent gate damage in the event that an
CXa
CXb
the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor.
The TPIC5401 is offered in a 16-pin thermally enhanced dual-in-line (NE) package and a 20-pin wide-body
surface-mount (DW) package and is characterized for operation over the case temperature range of –40°C to
125°C.
NE PACKAGE
(TOP VIEW)
DW PACKAGE
(TOP VIEW)
SOURCE1
DRAIN1
GATE1
DRAIN2
SOURCE2/GND
GATE2
GND
SOURCE4/GND
GATE4
SOURCE2/GND
GATE2
NC
1
2
3
4
5
6
7
8
16
15
14
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
13 GND
12 GND
GND
NC
NC
GND
DRAIN4
SOURCE3
DRAIN3
GATE3
DRAIN2
11
10
9
GATE3
GATE4
15 SOURCE1
DRAIN3
SOURCE3
14
13
12
11
SOURCE4/GND
DRAIN4
DRAIN1
GATE1
NC
NC
NC
NC
NC – No internal connection
schematic
DRAIN1
DRAIN3
Q1
Q3
Z1
D1
D2
Z3
GATE3
GATE1
Z
Z
Z
C3b
C1b
Z
SOURCE1
DRAIN2
C1a
C3a
SOURCE3
DRAIN4
Q2
Q4
GATE4
GATE2
Z
Z2
Z4
Z
Z
C4b
C2b
Z
C2a
C4a
GND, SOURCE2, SOURCE4
NOTE: For correct operation, no terminal pin may be taken below GND.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265