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ꢉꢊꢋꢌ ꢂꢍꢎ ꢏꢐ ꢎ ꢑꢀ ꢏꢊꢁꢌ ꢒꢀ ꢏ ꢃꢀꢏ ꢍꢐ ꢈꢒ ꢎꢂ ꢃ ꢊꢈ ꢏꢓ ꢏ ꢈ
ꢁꢒ ꢔ ꢏꢌꢐ ꢍꢕ ꢒꢖ ꢐꢑ ꢌꢌ ꢑꢗ
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SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
• Low r
. . . 0.4 Ω Typ
• Voltage Output . . . 60 V
DW PACKAGE
(TOP VIEW)
DS(on)
• Input Protection Circuitry . . . 18 V
• Pulsed Current . . . 3 A Per Channel
• Extended ESD Capability . . . 4000 V
• Direct Logic-Level Interface
GND
SOURCE2/GND
GATE2
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
SOURCE4/GND
GATE4
NC
NC
DRAIN4
SOURCE3
DRAIN3
GATE3
NC
DRAIN2
15 SOURCE1
description
14
13
12
11
DRAIN1
GATE1
NC
The TPIC5421L is a monolithic gate-protected
logic-level power DMOS array that consists of four
electrically isolated N-channel enhancement-
mode DMOS transistors, two of which are
configured with common source. Each transistor
features integrated high-current zener diodes
NC
NC
NE PACKAGE
(TOP VIEW)
(Z
and Z
) to prevent gate damage in the
CXa
CXb
SOURCE1
DRAIN1
GATE1
DRAIN2
SOURCE2/GND
GATE2
1
2
3
4
5
6
7
8
16
15
14
event that an overstress condition occurs. These
zener diodes also provide up to 4000 V of ESD
protection when tested using the human-body
model of a 100-pF capacitor in series with a 1.5-kΩ
resistor.
13 GND
12 GND
GND
GND
11
10
9
GATE3
GATE4
The TPIC5421L is offered in a 20-pin wide-body
surface-mount (DW) package and a 16-pin
thermally-enhanced dual-in-line (NE) package
and is characterized for operation over the case
temperature of −40°C to 125°C.
DRAIN3
SOURCE3
SOURCE4/GND
DRAIN4
NC − No internal connection
schematic
14
7
8
DRAIN1
GATE1
DRAIN3
GATE3
Q1
Q3
Z1
D1
D2
Z3
13
Z
C1b
Z
C3b
Z
6
Z
C1a
15
C3a
SOURCE3
DRAIN4
SOURCE1
16
5
DRAIN2
Q2
Q4
19
3
GATE4
GATE2
Z2
Z4
Z
Z
C2b
C4b
Z
C2a
Z
C4a
1, 2, 20
GND, SOURCE2, SOURCE4
NOTE A: For correct operation, no terminal may be taken below GND.
Pin numbers shown are for the DW package.
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Copyright 1995, Texas Instruments Incorporated
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1
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