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TPIC5223LDR PDF预览

TPIC5223LDR

更新时间: 2024-11-29 21:16:27
品牌 Logo 应用领域
德州仪器 - TI 开关光电二极管晶体管
页数 文件大小 规格书
13页 262K
描述
1000mA, 60V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MS-012AA, MS-012, 8 PIN

TPIC5223LDR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:MS-012, 8 PIN针数:8
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.84其他特性:ESD PROTECTED, LOGIC LEVEL COMPATIBLE
外壳连接:ISOLATED配置:SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE
最小漏源击穿电压:60 V最大漏极电流 (ID):1 A
最大漏源导通电阻:0.43 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):50 pFJEDEC-95代码:MS-012AA
JESD-30 代码:R-PDSO-G8元件数量:2
端子数量:8工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:N-CHANNEL功耗环境最大值:0.95 W
认证状态:Not Qualified表面贴装:YES
端子形式:GULL WING端子位置:DUAL
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

TPIC5223LDR 数据手册

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TPIC5223L  
2-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL  
POWER DMOS ARRAY  
SLIS043A – NOVEMBER 1994 – REVISED SEPTEMBER 1995  
D PACKAGE  
(TOP VIEW)  
Low r  
. . . 0.38 Typ  
DS(on)  
Voltage Output . . . 60 V  
Input Protection Circuitry . . . 18 V  
Pulsed Current . . . 3 A Per Channel  
Extended ESD Capability . . . 4000 V  
Direct Logic-Level Interface  
GND  
SOURCE1  
GATE2  
DRAIN1  
GATE1  
SOURCE2  
NC  
1
2
3
4
8
7
6
5
DRAIN2  
NC – No internal connection  
description  
The TPIC5223L is a monolithic gate-protected logic-level power DMOS array that consists of two electrically  
isolated independent N-channel enhancement-mode DMOS transistors. Each transistor features integrated  
high-current zener diodes (Z  
occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body  
and Z  
) to prevent gate damage in the event that an overstress condition  
CXa  
CXb  
model of a 100-pF capacitor in series with a 1.5-kresistor.  
The TPIC5223L is offered in a standard eight-pin small-outline surface-mount (D) package and is characterized  
for operation over the case temperature of 40°C to 125°C.  
schematic  
DRAIN1  
8
DRAIN2  
4
GATE2  
3
Q1  
Q2  
D1  
D2  
Z1  
Z2  
7
GATE1  
Z
C1b  
Z
Z
C2b  
Z
C1a  
C2a  
2
1
6
SOURCE1  
GND  
SOURCE2  
NOTE A: For correct operation, no terminal may be taken below GND.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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