TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
DGE PACKAGE
( TOP VIEW )
Organization . . . 512K × 16 × 2 Banks
3.3-V Power Supply (±10% Tolerance)
Two Banks for On-Chip Interleaving
(Gapless Accesses)
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
V
SS
DQ15
DQ14
CC
2
DQ0
DQ1
High Bandwidth – Up to 83-MHz Data Rates
3
CAS Latency (CL) Programmable to 2 or 3
Cycles From Column-Address Entry
4
V
V
SSQ
DQ13
DQ12
SSQ
DQ2
5
Burst Sequence Programmable to Serial or
Interleave
6
DQ3
7
V
V
CCQ
DQ11
DQ10
CCQ
DQ4
Burst Length Programmable to 1, 2, 4, 8, or
Full Page
8
9
DQ5
Chip Select and Clock Enable for
Enhanced-System Interfacing
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
V
SSQ
DQ9
DQ8
SSQ
DQ6
DQ7
Cycle-by-Cycle DQ-Bus Mask Capability
With Upper and Lower Byte Control
V
V
CCQ
CCQ
DQML
NC
DQMU
CLK
CKE
NC
A9
Auto-Refresh and Self-Refresh Capability
4K Refresh (Total for Both Banks)
W
CAS
RAS
CS
High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
Power-Down Mode
A11
A10
A0
Compatible With JEDEC Standards
Pipeline Architecture
A8
A7
Temperature Ranges:
Operating, 0°C to 70°C
Storage, – 55°C to 150°C
A1
A6
A2
A5
A3
A4
V
V
SS
CC
SYNCHRONOUS
CLOCK CYLE
TIME
ACCESS TIME
CLOCK TO
OUTPUT
REFRESH
INTERVAL
PIN NOMENCLATURE
A0–A10
Address Inputs
t
t
t
t
t
REF
CK3
CK2
AC3
AC2
‡
(CL = 3) (CL = 2)
(CL = 3)
(CL = 2)
A0–A10 Row Addresses
A0–A7 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
†
’626162-12A
12 ns
12 ns
15 ns
18 ns
9 ns
9 ns
64 ms
64 ms
’626162-12
9 ns
10 ns
A11
CAS
CKE
†
–12A speed device is supported only at –5/+10% V
CL = CAS latency
CC
‡
CLK
CS
System Clock
Chip Select
description
DQ0–DQ15
DQML, DQMU Data/Output Mask Enables
NC
RAS
SDRAM Data Input/Output
The TMS626162 device is
a
high-speed
16777216-bit synchronous dynamic random-
access memory (SDRAM) organized as two
banks of 524288 words with 16 bits per word.
No Connect
Row-Address Strobe
Power Supply (3.3-V Typ)
Power Supply for Output Drivers (3.3-V Typ)
Ground
Ground for Output Drivers
Write Enable
V
CC
V
CCQ
All inputs and outputs of the TMS626162 series
are compatible with the LVTTL interface.
V
SS
V
W
SSQ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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