5秒后页面跳转
捷配首页

Datasheet > TMS626162-12DGE
TMS626162-12DGE PDF预览

TMS626162-12DGE

更新时间： 2024-10-29 01:19:59
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
44页 659K
描述
524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

阅读下载

中文翻译

获取价格

TMS626162-12DGE 数据手册

 浏览型号TMS626162-12DGE的Datasheet PDF文件第2页浏览型号TMS626162-12DGE的Datasheet PDF文件第3页浏览型号TMS626162-12DGE的Datasheet PDF文件第4页浏览型号TMS626162-12DGE的Datasheet PDF文件第5页浏览型号TMS626162-12DGE的Datasheet PDF文件第6页浏览型号TMS626162-12DGE的Datasheet PDF文件第7页 
TMS626162  
524288 BY 16-BIT BY 2-BANK  
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY  
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997  
DGE PACKAGE  
( TOP VIEW )  
Organization . . . 512K × 16 × 2 Banks  
3.3-V Power Supply (±10% Tolerance)  
Two Banks for On-Chip Interleaving  
(Gapless Accesses)  
1
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
V
V
SS  
DQ15  
DQ14  
CC  
2
DQ0  
DQ1  
High Bandwidth – Up to 83-MHz Data Rates  
3
CAS Latency (CL) Programmable to 2 or 3  
Cycles From Column-Address Entry  
4
V
V
SSQ  
DQ13  
DQ12  
SSQ  
DQ2  
5
Burst Sequence Programmable to Serial or  
Interleave  
6
DQ3  
7
V
V
CCQ  
DQ11  
DQ10  
CCQ  
DQ4  
Burst Length Programmable to 1, 2, 4, 8, or  
Full Page  
8
9
DQ5  
Chip Select and Clock Enable for  
Enhanced-System Interfacing  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
V
V
SSQ  
DQ9  
DQ8  
SSQ  
DQ6  
DQ7  
Cycle-by-Cycle DQ-Bus Mask Capability  
With Upper and Lower Byte Control  
V
V
CCQ  
CCQ  
DQML  
NC  
DQMU  
CLK  
CKE  
NC  
A9  
Auto-Refresh and Self-Refresh Capability  
4K Refresh (Total for Both Banks)  
W
CAS  
RAS  
CS  
High-Speed, Low-Noise, Low-Voltage TTL  
(LVTTL) Interface  
Power-Down Mode  
A11  
A10  
A0  
Compatible With JEDEC Standards  
Pipeline Architecture  
A8  
A7  
Temperature Ranges:  
Operating, 0°C to 70°C  
Storage, – 55°C to 150°C  
A1  
A6  
A2  
A5  
A3  
A4  
V
V
SS  
CC  
SYNCHRONOUS  
CLOCK CYLE  
TIME  
ACCESS TIME  
CLOCK TO  
OUTPUT  
REFRESH  
INTERVAL  
PIN NOMENCLATURE  
A0–A10  
Address Inputs  
t
t
t
t
t
REF  
CK3  
CK2  
AC3  
AC2  
‡
(CL = 3) (CL = 2)  
(CL = 3)  
(CL = 2)  
A0–A10 Row Addresses  
A0–A7 Column Addresses  
A10 Automatic-Precharge Select  
Bank Select  
Column-Address Strobe  
Clock Enable  
†
’626162-12A  
12 ns  
12 ns  
15 ns  
18 ns  
9 ns  
9 ns  
64 ms  
64 ms  
’626162-12  
9 ns  
10 ns  
A11  
CAS  
CKE  
†
–12A speed device is supported only at –5/+10% V  
CL = CAS latency  
CC  
‡
CLK  
CS  
System Clock  
Chip Select  
description  
DQ0–DQ15  
DQML, DQMU Data/Output Mask Enables  
NC  
RAS  
SDRAM Data Input/Output  
The TMS626162 device is  
a
high-speed  
16777216-bit synchronous dynamic random-  
access memory (SDRAM) organized as two  
banks of 524288 words with 16 bits per word.  
No Connect  
Row-Address Strobe  
Power Supply (3.3-V Typ)  
Power Supply for Output Drivers (3.3-V Typ)  
Ground  
Ground for Output Drivers  
Write Enable  
V
CC  
V
CCQ  
All inputs and outputs of the TMS626162 series  
are compatible with the LVTTL interface.  
V
SS  
V
W
SSQ  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...44

中文翻译

下载PDF

与TMS626162-12DGE相关器件

型号 品牌 获取价格 描述 数据表
TMS626162-12DGER TI

获取价格

 		1MX16 SYNCHRONOUS DRAM, 9ns, PDSO50, TSOP-50
TMS626162-15 TI

获取价格

 		TMS626162-15
TMS626162-15DGE TI

获取价格

 		524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
TMS626162-15DGER TI

获取价格

 		1MX16 SYNCHRONOUS DRAM, PDSO50, TSOP-50
TMS626162A TI

获取价格

 		524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
TMS626162A-10DGE TI

获取价格

 		1MX16 SYNCHRONOUS DRAM, 7ns, PDSO50, PLASTIC, SOP-50
TMS626402-10DGE TI

获取价格

 		4MX4 SYNCHRONOUS DRAM, PDSO44, 0.400 INCH, PLASTIC, TSOPII-44
TMS626402-12DGE TI

获取价格

 		4MX4 SYNCHRONOUS DRAM, PDSO44, 0.400 INCH, PLASTIC, TSOPII-44
TMS626402-12DGE ROCHESTER

获取价格

 		4MX4 SYNCHRONOUS DRAM, PDSO44, 0.400 INCH, PLASTIC, TSOPII-44
TMS626402-15DGE TI

获取价格

 		4MX4 SYNCHRONOUS DRAM, PDSO44, 0.400 INCH, PLASTIC, TSOPII-44

与TMS626162-12DGE相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证