Datasheet > SY89801A

SY89801A

更新时间： 2024-11-04 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
5页	85K
描述
HP PA-8000 CLOCK SOURCE

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数据手册

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SY89801A 数据手册

ClockWorks™

PRELIMINARY

SY89801A

HP PA-8000

CLOCK SOURCE

FEATURES

DESCRIPTION

■ 3.3V, –1.9V power suppies

Micrel-Synergy's SY89801A PLL based clock generator

provides,inasinglechip,allthenecessaryclocksforHewlett-

Packard's PA-8000 Microprocessor.

■ Differential LVPECL clock input

■ Differential HSTL/LVPECL outputs

■ Compatible with HP PA-8000 microprocessors

Utilizing Micrel-Synergy's advanced PLL technology, the

SY89801A accepts a Positive-ECL (PECL) reference clock

input at 100MHz-132MHz, and provides precisely aligned,

ultra-low-jitterratiosoffrequenciesnecessaryfortheoperation

of the processor. In addition, the SY89801A provides the

"USYNC" synchronizing signals as required by the PA-8000.

The frequency ratios are 1:1, 4:3, 3:2, 5:3 and 2:1.

TofacilitatedirectinterfacingtothePA-8000,theSY89801A

operatesacross+3.3voltand-1.9 voltsupplies.Theprocessor

clock(PCLK), runwayclock(RCLK), andUSYNCoutputsare

HSTL-compatible. Additionally, there is a PECL-compatible

runwayclockoutput(RCLKLV). TheSY89801Arequiresonly

a simple external series-RC loop filter.

■ Low-jitter source for all PA-8000 required timing

signals

■ Available in 44-pin MQUAD package

PIN CONFIGURATION

Coupling Micrel-Synergy's advanced PLL technology with

our proprietary ASSET bipolar process has produced a

Timing Generator IC which meets the stringent requirements

of the PA-8000 µP, while setting a new standard for

performance and flexibility.

1 44 43 42 41 40

VEEA

VEE

PCLK1

PCLK2

FILP

FILN

VCCA

PCLK2

VCC

TOP VIEW

MQUAD

M44-1

USYNC

VCC

18 19 20 21 22 23 24 25 26 27 28

PIN NAMES

REF_CLK, REF_CLK

FILP, FILN

Function

Differential Input Ref. Clock

Filter Pins (Positive & Negative)

Analog VCC, VEE

VCCA, VEEA

RST

Master Reset

FSEL2-0

LVPECL Frequency Select Pins

Diff. HSTL Sync Signal for PA-8000

Diff. HSTL Processor Clock Signal

Diff. HSTL Runway Clock Signal

Diff. LVPECL Clock Signal

USYNC, USYNC

PCLK1-2, PCLK1-2

RCLK, RCLK

RCLKLV, RCLKLV

Rev.: E

Amendment: /0

Issue Date: November 1998

12 3 4 5

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SY89808LTG	MICREL	获取价格	3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89808LTGTR	MICREL	获取价格	3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
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SY89808LTITR	MICREL	获取价格	3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89809	MICREL	获取价格	3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER
SY89809AL	MICREL	获取价格	3.3V LVPECL/HSTL to HSTL 1:9 High-