SY89809L

更新时间： 2024-11-04 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		时钟驱动器
页数	文件大小	规格书
4页	81K
描述
3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SY89809L 数据手册

3.3V 1:9 HIGH-PERFORMANCE,

LOW-VOLTAGE

BUS CLOCK DRIVER

ClockWorks™

SY89809L

FEATURES

DESCRIPTION

■ 3.3V core supply, 1.8V output supply for reduced

The SY89809L is a High-Performance Bus Clock Driver

with 9 differential HSTL (High-Speed Transceiver Logic)

output pairs. The part is designed for use in low-voltage

(3.3V/1.8V) applications which require a large number of

outputs to drive precisely aligned, ultralow skew signals to

their destination. The input is multiplexed from either HSTL

or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic)

by the CLK_SEL pin. The Output Enable (OE) is

synchronous so that the outputs will only be enabled/

disabled when they are already in the LOW state. This

avoids any chance of generating a runt clock pulse when

the device is enabled/disabled as can happen with an

asynchronous control.

power

■ LVPECL and HSTL inputs

■ 9 differential HSTL (low-voltage swing) output pairs

■ HSTL outputs drive 50Ω to ground with no

offset voltage

■ 500MHz maximum clock frequency

■ Low part-to-part skew (200ps max.)

■ Low pin-to-pin skew (50ps max.)

■ Available in 32-pin TQFP package

The SY89809L features low pin-to-pin skew (50ps max.)

and low part-to-part skew (200ps max.)—performance

previously unachievable in a standard product having such

a high number of outputs. The SY89809L is available in a

single space saving package, enabling a lower overall cost

solution.

PIN CONFIGURATION

32 31 30 29 28 27 26 25

VCCO

VCCI

HSTL_CLK

CLK_SEL

APPLICATIONS

Top View

TQFP

T32-1

■ High-performance PCs

■ Workstations

LVPECL_CLK

GND

■ Parallel processor-based systems

■ Other high-performance computing

■ Communications

VCCO

10 11 12 13 14 15 16

PIN NAMES

LOGIC SYMBOL

Function

Differential HSTL Inputs

LVPECL_CLK, /LVPECL_CLK Differential LVPECL Inputs

CLK_SEL

HSTL_CLK, /HSTL_CLK

HSTL_CLK

CLK_SEL

Input CLK Select (LVTTL)

Output Enable (LVTTL)

Differential HSTL Outputs

Ground

Q0 – Q8

LVPECL_CLK

Q₀-Q₈, /Q₀-/Q₈

GND

LEN

LVPECL_CLK

V_CCI

V_CCCore

V_CCO

V_CCOutput

Rev.: A

Amendment: /0

Issue Date: March 2000

12 3 4

中文翻译

下载PDF

与SY89809L相关器件

型号	品牌	获取价格	描述	数据表
SY89809L_05	MICREL	获取价格	3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER
SY89809L_09	MICREL	获取价格	3.3V 1:9 High-Performance, Low-Voltage Bus Clock Driver
SY89809LHH	MICROCHIP	获取价格	IC,1:9 OUTPUT, DIFFERENTIAL,TQFP,32PIN,PLASTIC
SY89809LHH-TR	MICROCHIP	获取价格	LOW SKEW CLOCK DRIVER
SY89809LTC	MICREL	获取价格	3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER
SY89809LTC	MICROCHIP	获取价格	Low Skew Clock Driver
SY89809LTCTR	MICREL	获取价格	3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER
SY89809LTH	MICREL	获取价格	3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER
SY89809LTH	MICROCHIP	获取价格	89809 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
SY89809LTHTR	MICREL	获取价格	3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER

与SY89809L相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

SY89809L

SY89809L 数据手册

与SY89809L相关器件

与SY89809L相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SY89809L

SY89809L 数据手册

与SY89809L相关器件

与SY89809L相关文章

您还可以找

您在本页遇到什么问题？