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SY89809L_05 PDF预览

SY89809L_05

更新时间: 2024-11-05 04:30:07
品牌 Logo 应用领域
麦瑞 - MICREL 时钟驱动器
页数 文件大小 规格书
7页 104K
描述
3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER

SY89809L_05 数据手册

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®  
®
3.3V 1:9 HIGH-PERFORMANCE,  
Precision Edge  
LOW-VOLTAGE BUS CLOCK DRIVER  
SY89809L  
FEATURES  
3.3V core supply, 1.8V output supply for reduced  
®
Precision Edge  
power  
LVPECL and HSTL inputs  
9 differential HSTL (low-voltage swing) output pairs  
DESCRIPTION  
HSTL outputs drive 50to ground with no  
The SY89809L is a High-Performance Bus Clock Driver  
with 9 differential HSTL (High-Speed Transceiver Logic)  
output pairs. The part is designed for use in low-voltage  
(3.3V/1.8V) applications which require a large number of  
outputs to drive precisely aligned, ultralow skew signals to  
their destination. The input is multiplexed from either HSTL  
or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic)  
by the CLK_SEL pin. The Output Enable (OE) is  
synchronous so that the outputs will only be enabled/  
disabled when they are already in the LOW state. This  
avoids any chance of generating a runt clock pulse when  
the device is enabled/disabled as can happen with an  
asynchronous control.  
offset voltage  
500MHz maximum clock frequency  
Low part-to-part skew (200ps max.)  
Low pin-to-pin skew (50ps max.)  
Available in 32-pin TQFP package  
LOGIC SYMBOL  
CLK_SEL  
The SY89809L features low pin-to-pin skew (50ps max.)  
and low part-to-part skew (200ps max.)—performance  
previously unachievable in a standard product having such  
a high number of outputs. The SY89809L is available in a  
single space saving package, enabling a lower overall cost  
solution.  
HSTL_CLK  
0
/HSTL_CLK  
9
Q0 Q8  
9
/Q0 /Q8  
LVPECL_CLK  
1
LEN  
D
/LVPECL_CLK  
Q
OE  
APPLICATIONS  
High-performance PCs  
Workstations  
Parallel processor-based systems  
Other high-performance computing  
Communications  
TRUTH TABLE  
SIGNAL GROUPS  
OE(1)  
CLK_SEL  
Q0 – Q8  
LOW  
/Q0 – /Q8  
HIGH  
Level  
HSTL  
Direction  
Input  
Signal  
0
0
1
1
0
1
0
1
HSTL_CLK, /HSTL_CLK  
Q0 Q8, /Q0 /Q8  
LOW  
HIGH  
HSTL  
Output  
Input  
HSTL_CLK  
LVPECL_CLK  
/HSTL_CLK  
/LVPECL_CLK  
LVPECL  
LVPECL_CLK, /LVPECL_CLK  
CLK_SEL, OE  
LVCMOS/LVTTL  
Input  
Note:  
1. The OE (output enable) signal is synchronized with the low level of the  
HSTL_CLK and LVPECL_CLK signal.  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: E  
Amendment: /0  
M9999-092005  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: September 2005  

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