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SY89823L

更新时间： 2024-11-06 14:53:39
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
8页 122K
描述
The SY89823L is a high-performance bus clock driver with 22 differential High-Speed Transceiver Lo

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SY89823L 数据手册

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®  
3.3V, 500MHz 1:22  
DIFFERENTIAL HSTL (1.5V)  
FANOUT BUFFER/TRANSLATOR  
®
L  
Precision Edge  
SY89823L  
FEATURES  
■ 22 differential HSTL (low-voltage swing) output pairs  
®
Precision Edge  
■ HSTL outputs drive 50Ω to ground with no offset  
voltage  
DESCRIPTION  
■ 3.3V core supply, 1.8V output supply for reduced  
power  
The SY89823L is a high-performance bus clock driver with 22  
differential High-Speed Transceiver Logic (HSTL), 1.5V compatible  
output pairs. The device is designed for use in low-voltage (3.3V/  
1.8V) applications that require a large number of outputs to drive  
precisely aligned, ultra-low skew signals to their destination. The  
input is multiplexed from either HSTL or Low-Voltage Positive-  
Emitter-Coupled Logic (LVPECL) by the CLK_SEL pin.  
■ LVPECL and HSTL inputs  
■ Low part-to-part skew (200ps max.)  
■ Low pin-to-pin skew (50ps max.)  
■ Triple-buffered output enable (OE)  
■ –40°C to +85°C temperature range  
■ Available in a 64-pin EPAD-TQFP  
The Output Enable (OE) is synchronous and triple-buffered so  
that the outputs will only be enabled/disabled when they are already  
in the LOW state. This avoids any potential of generating a runt clock  
pulse when the device is enabled/disabled, as can occur with an  
asynchronous control. The triple-buffering feature provides a three-  
clock delay from the time the OE input is asserted/de-asserted to  
when the clock appears at the outputs.  
APPLICATIONS  
■ High-performance PCs  
■ Workstations  
The SY89823L features low pin-to-pin skew (50ps max.) and low  
part-to-partskew (200psmax.),performancepreviouslyunachievable  
in a standard product having such a high number of outputs. The  
SY89823L is available in a single, space-saving package, enabling  
a lower overall cost solution.  
■ Parallel processor-based systems  
■ Other high-performance computing  
■ Communications  
All support documentation can be found on Micrel’s web site at:  
www.micrel.com.  
LOGIC SYMBOL  
TRUTH TABLE  
OE(1)  
CLK_SEL  
Q0-Q21  
LOW  
/Q0-/Q21  
HIGH  
CLK_SEL  
0
0
1
1
0
1
0
1
HSTL_CLK  
/HSTL_CLK  
0
LOW  
HIGH  
22  
HSTL_CLK  
LVPECL_CLK  
/HSTL_CLK  
/LVPECL_CLK  
Q0 - Q21  
22  
/Q0 - /Q21  
LVPECL_CLK  
1
Note:  
1. The output enable (OE) signal is synchronized with the low level of the  
EN  
/LVPECL_CLK  
HSTL_CLK and LVPECL_CLK signal.  
ENABLE  
LOGIC  
OE  
TYPICAL PERFORMANCE  
Output Amplitude  
vs. Frequency  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
0
0.2 0.4 0.6 0.8  
1 1.2 1.4 1.6  
OUTPUT FREQUENCY (GHz)  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: D  
Amendment: /0  
M9999-091908  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: September 2008  
12345678

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SY89823L_08 MICREL

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 		3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89823LHC MICREL

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 		3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89823LHCTR MICREL

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 		3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89823LHH MICROCHIP

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 		Low Skew Clock Driver, 89823 Series, 22 True Output(s), 0 Inverted Output(s), PQFP64, LEAD
SY89823LHH MICREL

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 		Low Skew Clock Driver, 89823 Series, 22 True Output(s), 0 Inverted Output(s), PQFP64, LEAD
SY89823LHI MICREL

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 		3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89823LHITR MICREL

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 		3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89823LHY MICREL

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 		3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89823LHYTR MICREL

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 		3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89823LHZ MICREL

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 		3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR

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