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SY89825UHI PDF预览

SY89825UHI

更新时间: 2024-11-04 22:18:55
品牌 Logo 应用领域
麦瑞 - MICREL 时钟驱动器逻辑集成电路
页数 文件大小 规格书
8页 62K
描述
2.5/3.3V 1:22 HIGH-PERFORMANCE, LOW-VOLTAGE PECL BUS CLOCK DRIVER & TRANSLATOR w/ INTERNAL TERMINATION

SY89825UHI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:HTFQFP, TQFP64,.47SQ针数:64
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.79其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:89825输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:64
实输出次数:22最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HTFQFP封装等效代码:TQFP64,.47SQ
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):240电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:1.4 ns传播延迟(tpd):1.4 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.035 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.37 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
最小 fmax:2000 MHzBase Number Matches:1

SY89825UHI 数据手册

 浏览型号SY89825UHI的Datasheet PDF文件第2页浏览型号SY89825UHI的Datasheet PDF文件第3页浏览型号SY89825UHI的Datasheet PDF文件第4页浏览型号SY89825UHI的Datasheet PDF文件第5页浏览型号SY89825UHI的Datasheet PDF文件第6页浏览型号SY89825UHI的Datasheet PDF文件第7页 
2.5/3.3V 1:22 HIGH-PERFORMANCE,  
LOW-VOLTAGE PECL BUS CLOCK DRIVER  
& TRANSLATOR w/ INTERNAL TERMINATION  
ClockWorks™  
SY89825U  
FINAL  
FEATURES  
DESCRIPTION  
LVPECL or LVDS input to 22 LVPECL outputs  
100K ECL compatible outputs  
The SY89825U is a High Performance Bus Clock Driver  
with 22 differential LVPECL output pairs. This part is  
designed for use in low voltage (2.5V, 3.3V) applications  
which require a large number of outputs to drive precisely  
aligned, ultra low skew signals to their destination. The  
input is multiplexed from either LVDS or LVPECL by the  
CLK_SEL pin. The LVDS input includes a 100internal  
termination, thus eliminating the need for external  
termination. The Output Enable (OE) is synchronous so  
that the outputs will only be enabled/disabled when they  
are already in the LOW state. This eliminates any chance  
of generating a runt clock pulse when the device is enabled/  
disabled as can happen with an asynchronous control.  
The SY89825U features low pin-to-pin skew (35ps max.)  
—performance previously unachievable in a standard  
product having such a high number of outputs. The  
SY89825U is available in a single space saving package  
which provides a lower overall cost solution. In addition, a  
single chip solution improves timing budgets by eliminating  
the multiple device solution with their corresponding large  
part-to-part skew.  
LVDS input includes 100termination  
Guaranteed AC parameters over voltage:  
• > 2GHz fMAX (toggle)  
• < 35ps max. ch-ch skew  
Low voltage operation: 2.5V, 3.3V  
Temperature range: –40°C to +85°C  
Output enable pin  
Available in a 64-Pin EPAD-TQFP  
PIN CONFIGURATION  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
VCCO  
NC  
NC  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
VCCO  
Q7  
/Q7  
Q8  
/Q8  
VCCI  
APPLICATIONS  
LVDS_CLK  
/LVDS_CLK  
CLK_SEL  
LVPECL_CLK  
/LVPECL_CLK  
GND  
Q9  
/Q9  
64-Pin  
EPAD-TQFP  
(Top View)  
High-performance PCs  
Workstations  
Q10  
/Q10  
Q11  
/Q11  
Q12  
/Q12  
Q13  
/Q13  
VCCO  
9
10  
11  
12  
13  
14  
15  
16  
OE  
NC  
NC  
/Q21  
Q21  
VCCO  
Parallel processor-based systems  
Other high-performance computing  
Communications  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
Rev.:  
A
Amendment: /0  
Issue Date: September 2001  
1

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