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SY89827L_10 PDF预览

SY89827L_10

更新时间: 2024-11-05 08:56:27
品牌 Logo 应用领域
麦瑞 - MICREL 复用器输入元件
页数 文件大小 规格书
11页 536K
描述
3.3V 500MHz DUAL 1:10 HSTL FANOUT BUFFER/TRANSLATOR WITH 2:1 MUX INPUT

SY89827L_10 数据手册

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®
L  
3.3Vꢀ500MHzꢀDUALꢀ1:10ꢀHSTLꢀFANOUT  
Precision Edge  
SY89827L  
BUFFER/TRANSLATORꢀWITHꢀ2:1ꢀMUXꢀINPUT  
FEATURES  
Dual LVPECL or HSTL input, 10 differential 1.5V  
HSTL compatible outputs  
®
Precision Edge  
ꢀ Configurableꢀasꢀdual-channelꢀ10ꢀoutputꢀorꢀaꢀsingle-  
channelꢀ20ꢀoutputꢀclockꢀdriver  
DESCRIPTION  
ꢀ GuaranteedꢀACꢀparametersꢀoverꢀtemperatureꢀandꢀ  
voltage:  
•ꢀ >ꢀ500MHzꢀf  
•ꢀ <ꢀ50psꢀwithinꢀdeviceꢀskew  
•ꢀ <ꢀ1.5nsꢀpropagationꢀdelay  
The SY89827L is a High Performance Bus Clock  
Driver with dual 1:10 or single 1:20 HSTL (High Speed  
Transceiver Logic) output pairs. The part is designed for  
use in low voltage (3.3V/1.8V) applications which require a  
large number of outputs to drive precisely aligned, ultra low  
skew signals to their destination. The input is multiplexed  
from either HSTL or LVPECL (Low Voltage Positive Emitter  
Coupled Logic) by the CLK_SEL pin. The Output Enables  
(OE1 & OE2) are synchronous so that the outputs will only  
be enabled/disabled when they are already in the LOW state.  
This avoids any chance of generating a runt clock pulse  
when the device is enabled/disabled as can happen with an  
asynchronous control.  
MAX  
•ꢀ <ꢀ700psꢀt / t time  
r
f
ꢀ Lowꢀjitterꢀdesign  
•ꢀ 186fs ꢀphaseꢀjitter  
RMS  
ꢀ 3.3Vꢀcoreꢀsupply,ꢀ1.8Vꢀoutputꢀsupply  
Output enable function  
ꢀ Availableꢀinꢀaꢀ64-PinꢀEPAD-TQFP  
The SY89827L features extremely low skew performance  
of <50ps over temperature and voltage –performance  
previously unachievable in a standard product having such  
a high number of outputs. The SY89827L is available in a  
single space saving package, enabling a lower overall cost  
solution. For applications that require greater HSTL fanout  
capability, consider the SY89824L.  
APPLICATIONS  
ꢀ High-performanceꢀPCs  
ꢀ Workstations  
ꢀ Parallelꢀprocessor-basedꢀsystems  
ꢀ Otherꢀhigh-performanceꢀcomputing  
Communications  
TYPICALꢀAPPLICATIONꢀCIRCUIT  
10  
PrimaryꢀClockꢀSource  
LVPECL_CLKA  
Primary  
Card  
10  
/LVPECL_CLKA  
RedundantꢀBackup  
ClockꢀSource  
10  
10  
LVPECL_CLKB  
Redundant  
Card  
/LVPECL_CLKB  
SEL1  
Primary/Backup Clock Select  
(Switchover within 2.0ns)  
System using SY89827L as a switchover circuit from a Primary Clock to a Redundant Backup Clock in a failsafe application.  
LVPECL inputs only, shown in this application.  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: F  
Amendment: /0  
M9999-073010  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: July 2010  

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