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SY89828L PDF预览

SY89828L

更新时间: 2024-11-09 04:30:07
品牌 Logo 应用领域
麦瑞 - MICREL 输入元件
页数 文件大小 规格书
13页 129K
描述
3.3V 1GHz DUAL 1:10 PRECISION LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX

SY89828L 数据手册

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®  
3.3V 1GHz DUAL 1:10 PRECISION  
LVDS FANOUT BUFFER/  
TRANSLATOR WITH 2:1 INPUT MUX  
®
Precision Edge  
SY89828L  
FEATURES  
High-performance dual 1:10, 1GHz LVDS fanout  
®
Precision Edge  
buffer/translator  
Two banks of 10 differential LVDS outputs  
DESCRIPTION  
Guaranteed AC parameters over temperature and  
voltage:  
• > 1GHz f  
• < 50ps within device skew  
• < 400ps t , t time  
The SY89828L is a precision fanout buffer with 20  
differential LVDS (Low Voltage Differential Swing) output  
pairs. The part is designed for use in low voltage 3.3V  
applications that require a large number of outputs to drive  
precisely aligned, ultra low-skew signals to their destination.  
The input is multiplexed from either LVDS or LVPECL (Low  
Voltage Positive Emitter Coupled Logic) by the CLK_SEL1  
and CLK_SEL2 pins. The Output Enables (OE1 and OE2)  
are synchronous so that the outputs will only be enabled/  
disabled when they are already in the LOW state. This  
avoids any chance of generating a runt clock pulse when  
the device is enabled/disabled as can happen with an  
asynchronous control.  
MAX  
r
f
Each bank includes a 2:1 input mux  
2:1 mux input accepts LVDS and LVPECL  
Low jitter performance  
• < 1ps  
cycle-to-cycle jitter  
RMS  
• < 1ps total jitter  
PP  
3.3V supply voltage  
Output enable function  
LVDS input includes internal 100termination  
Available in a 64-Pin EPAD-TQFP  
The SY89828L features a low pin-to-pin skew of less  
than 50ps—performance previously unachievable in a  
standard product having such a high number of outputs.  
The SY89828L is available in a single space saving package,  
enabling a lower overall cost solution.  
APPLICATIONS  
Enterprise networking  
High-end servers  
Communications  
TYPICAL APPLICATION CIRCUIT  
100  
100Ω  
5
5
Primary Clock Source  
LVDS_CLKA  
Primary  
Card  
/LVDS_CLKA  
Backup Clock Source  
5
5
LVDS_CLKB  
Redundant  
Card  
/LVDS_CLKB  
SEL1  
Primary/Backup Clock Select  
(Switchover with 2.0ns)  
System using SY89828L as a switchover circuit from a Primary Clock to a Redundant backup Clock in a fail-safe application.  
LVPECL inputs not shown in this application.  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: C  
Amendment: /0  
M9999-011907  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: January 2007  

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