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SY89827LHY-TR PDF预览

SY89827LHY-TR

更新时间: 2024-10-01 13:14:11
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麦瑞 - MICREL 复用器输入元件
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SY89827LHY-TR 数据手册

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®  
®
3.3V 500MHz DUAL 1:10 HSTL FANOUT  
Precision Edge  
SY89827L  
BUFFER/TRANSLATOR WITH 2:1 MUX INPUT  
FEATURES  
Dual LVPECL or HSTL input, 10 differential 1.5V  
®
HSTL compatible outputs  
Precision Edge  
Configurable as dual-channel 10 output or a single-  
channel 20 output clock driver  
DESCRIPTION  
Guaranteed AC parameters over temperature and  
voltage:  
• > 500MHz f  
• < 50ps within device skew  
• < 1.5ns propagation delay  
• < 700ps t / t time  
The SY89827L is a High Performance Bus Clock Driver  
with dual 1:10 or single 1:20 HSTL (High Speed  
Transceiver Logic) output pairs. The part is designed for  
use in low voltage (3.3V/1.8V) applications which require  
a large number of outputs to drive precisely aligned, ultra  
low skew signals to their destination. The input is  
multiplexed from either HSTL or LVPECL (Low Voltage  
Positive Emitter Coupled Logic) by the CLK_SEL pin.  
The Output Enables (OE1 & OE2) are synchronous so  
that the outputs will only be enabled/disabled when they  
are already in the LOW state. This avoids any chance of  
generating a runt clock pulse when the device is enabled/  
disabled as can happen with an asynchronous control.  
The SY89827L features extremely low skew  
performance of <50ps over temperature and voltage –  
performance previously unachievable in a standard  
product having such a high number of outputs. The  
SY89827L is available in a single space saving package,  
enabling a lower overall cost solution. For applications  
that require greater HSTL fanout capability, consider the  
SY89824L.  
MAX  
r
f
Low jitter design  
• < 1ps cycle-to-cycle jitter  
RMS  
• < 10ps total jitter  
PP  
3.3V core supply, 1.8V output supply  
Output enable function  
Available in a 64-Pin EPAD-TQFP  
APPLICATIONS  
High-performance PCs  
Workstations  
Parallel processor-based systems  
Other high-performance computing  
Communications  
TYPICAL APPLICATION CIRCUIT  
10  
Primary Clock Source  
LVPECL_CLKA  
Primary  
Card  
10  
/LVPECL_CLKA  
Redundant Backup  
Clock Source  
10  
10  
LVPECL_CLKB  
Redundant  
Card  
/LVPECL_CLKB  
SEL1  
Primary/Backup Clock Select  
(Switchover within 2.0ns)  
System using SY89827L as a switchover circuit from a Primary Clock to a Redundant Backup Clock in a failsafe application.  
LVPECL inputs only, shown in this application.  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: E  
Amendment: /0  
M9999-011907  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: January 2007  

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