Datasheet > SY89826L

SY89826L

更新时间： 2024-10-01 04:30:07

品牌	Logo	应用领域
麦瑞 - MICREL		输入元件
页数	文件大小	规格书
10页	122K
描述
3.3V 1GHz PRECISION 1:22 LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX

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SY89826L 数据手册

ꢀ

3.3V supply voltage

Precision Edge^®

SY89826L

3.3V 1GHz PRECISION 1:22 LVDS

FANOUT BUFFER/TRANSLATOR

WITH 2:1 INPUT MUX

Micrel, Inc.

Precision Edge

SY89826L

FEATURES

■ High-performance, 1GHz LVDS fanout buffer/

Precision Edge

translator

■ 22 differential LVDS output pairs

DESCRIPTION

■ Guaranteed AC parameters over temperature and

voltage:

The SY89826L is a precision fanout buffer with 22

differential LVDS (Low Voltage Differential Swing) output

pairs. The part is designed for use in low voltage 3.3V

applications that require a large number of outputs to drive

precisely aligned, ultra low-skew signals to their destination.

The input is multiplexed from either LVDS or LVPECL (Low

Voltage Positive Emitter Coupled Logic) by the CLK_SEL

pin. The OE (Output Enable) is synchronous so that the

outputs will only be enabled/disabled when they are already

in the LOW state. This avoids any chance of generating a

runt clock pulse when the device is enabled/disabled as

can happen with an asynchronous control.

The SY89826L features a low pin-to-pin skew of less

than 50ps—performance previously unachievable in a

standard product having such a high number of outputs.

The SY89826L is available in a single space saving package,

enabling a lower overall cost solution.

• > 1GHz f

• < 50ps within device skew

• < 400ps t / t time

MAX

■ Low jitter performance

• < 1ps (rms) cycle-to-cycle jitter

• < 1ps (pk-pk) total jitter

■ 2:1 mux input accepts LVDS and LVPECL

■ LVDS input includes internal 100Ω termination

■ Output enable function

■ Available in a 64-Pin EPAD-TQFP

APPLICATIONS

■ Enterprise networking

■ High-end servers

■ Communications

TRUTH TABLE

FUNCTIONAL BLOCK DIAGRAM

OE⁽¹⁾

CLK_SEL

Q0 – Q21

LOW

/Q0 – /Q21

HIGH

100Ω internal input

termination

22 LVDS compatible

outputs

CLK_SEL

LOW

HIGH

LVDS_CLK

/LVDS_CLK

LVDS_CLK

LVPECL_CLK

/LVDS_CLK

/LVPECL_CLK

Q0 - Q21

/Q0 - /Q21

NOTE:

1. The OE (output enable) signal is synchronized with the low level of the

LVDS_CLK and LVPECL_CLK signal.

LVPECL_CLK

/LVPECL_CLK

LEN

Precision Edge is a registered trademark of Micrel, Inc.

Rev.: D

Amendment: /0

M9999-011907

hbwhelp@micrel.com or (408) 955-1690

Issue Date: January 2007

12 3 4 5 6 7...10

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与SY89826L相关器件

型号	品牌	获取价格	描述	数据表
SY89826LHI	MICREL	获取价格	3.3V 1GHz PRECISION 1:22 LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX
SY89826LHI	MICROCHIP	获取价格	Low Skew Clock Driver, 89826 Series, 22 True Output(s), 0 Inverted Output(s), PQFP64, TQFP
SY89826LHITR	MICREL	获取价格	3.3V 1GHz PRECISION 1:22 LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX
SY89826LHY	MICREL	获取价格	3.3V 1GHz PRECISION 1:22 LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX
SY89826LHY	MICROCHIP	获取价格	89826 SERIES, LOW SKEW CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
SY89826LHYTR	MICREL	获取价格	3.3V 1GHz PRECISION 1:22 LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX
SY89826LHY-TR	MICROCHIP	获取价格	89826 SERIES, LOW SKEW CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
SY89827L	MICREL	获取价格	3.3V 500MHz DUAL 1:10 HSTL FANOUT BUFFER/TRANSLATOR WITH 2:1 MUX INPUT
SY89827L_10	MICREL	获取价格	3.3V 500MHz DUAL 1:10 HSTL FANOUT BUFFER/TRANSLATOR WITH 2:1 MUX INPUT
SY89827LHG	MICREL	获取价格	Low Skew Clock Driver, 89827 Series, 20 True Output(s), 0 Inverted Output(s), PQFP64, LEAD

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