SY89808LTGTR

更新时间： 2024-10-01 04:30:07

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
8页	132K
描述
3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR

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SY89808LTGTR 数据手册

Precision Edge^®

3.3V, 500MHz, 1:9 DIFFERENTIAL

HSTL (1.5V) FANOUT BUFFER/

TRANSLATOR

Micrel, Inc.

SY89808L

Precision Edge

SY89808L

FEATURES

■ 9 differential HSTL (1.5V compatible) output pairs

■ 500MHz maximum clock frequency

■ Triple-buffered enable function

Precision Edge

DESCRIPTION

■ 3.3V core supply, 1.8V output supply for reduced

power

The SY89808L is a High-Performance Bus Clock Driver with

9 differential HSTL (High-Speed Transceiver Logic) 1.5V

compatible output pairs. The part is designed for use in low-

voltage (3.3V/1.8V) applications which require a large number

of outputs to drive precisely aligned, ultra-low skew signals to

their destination. The input is multiplexed from either HSTL or

LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the

CLK_SEL pin.

■ LVPECL and HSTL inputs

■ HSTL outputs drive 50Ω to ground with no

offset voltage

■ Low pin-to-pin skew (25ps max.)

■ Guaranteed over industrial –40°C to +85°C

temperature range

■ Available in 32-pin TQFP package

The Output Enable (OE) is synchronous and triple-buffered

so that the outputs will only be enabled/disabled when they are

alreadyintheLOWstate.Thisavoidsanypotentialofgenerating

a runt clock pulse when the device is enabled/disabled, as can

occur with an asynchronous control. The triple-buffering feature

provides a three-clock delay from the time the OE input is

asserted/de-asserted to when the clock appears at the outputs.

APPLICATIONS

■ Workstations

■ Parallel processor-based systems

■ High-performance computing

■ Communications

The SY89808L features an ultra-low pin-to-pin skew of less

than 25ps. The SY89808L is available in a 32-TQFP space

saving package, enabling a lower overall cost solution.

TRUTH TABLE

OE⁽¹⁾

CLK_SEL

Q₀– Q₈

LOW

/Q₀– /Q₈

HIGH

LOGIC SYMBOL

LOW

HIGH

CLK_SEL

HSTL_CLK

LVPECL_CLK

/HSTL_CLK

/LVPECL_CLK

HSTL_CLK

/HSTL_CLK

Notes:

Q0 — Q8

1. The OE (output enable) signal is synchronized with the low level of the

HSTL_CLK and LVPECL_CLK signal.

/Q0 — /Q8

LVPECL_CLK

TYPICAL PERFORMANCE

/LVPECL_CLK

ENABLE

LOGIC

Output Amplitude

vs. Frequency

900

800

700

600

500

400

300

200

FREQUENCY (MHz)

Precision Edge is a registered trademark of Micrel, Inc.

Rev.: E

Amendment: /0

M9999-091405

hbwhelp@micrel.com or (408) 955-1690

Issue Date: September 2005

12 3 4 5 6 7 8

中文翻译

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与SY89808LTGTR相关器件

型号	品牌	获取价格	描述	数据表
SY89808LTI	MICREL	获取价格	3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89808LTITR	MICREL	获取价格	3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
SY89809	MICREL	获取价格	3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER
SY89809AL	MICREL	获取价格	3.3V LVPECL/HSTL to HSTL 1:9 High-
SY89809AL	MICROCHIP	获取价格	The SY89809AL is a high-performance bus clock driver with nine differential High-Speed Tra
SY89809ALTZ	MICROCHIP	获取价格	89809 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
SY89809ALTZTR	MICREL	获取价格	89809 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD
SY89809ALTZ-TR	MICROCHIP	获取价格	89809 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
SY89809L	MICREL	获取价格	3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER
SY89809L_05	MICREL	获取价格	3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER

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