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SY89809ALTZ PDF预览

SY89809ALTZ

更新时间: 2024-11-05 19:48:31
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
8页 286K
描述
89809 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32

SY89809ALTZ 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TQFP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:10 weeks
风险等级:5.35系列:89809
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:2
功能数量:1反相输出次数:
端子数量:32实输出次数:9
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TQFP
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):1.11 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:OTHER
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:7 mm
Base Number Matches:1

SY89809ALTZ 数据手册

 浏览型号SY89809ALTZ的Datasheet PDF文件第2页浏览型号SY89809ALTZ的Datasheet PDF文件第3页浏览型号SY89809ALTZ的Datasheet PDF文件第4页浏览型号SY89809ALTZ的Datasheet PDF文件第5页浏览型号SY89809ALTZ的Datasheet PDF文件第6页浏览型号SY89809ALTZ的Datasheet PDF文件第7页 
SY89809AL  
3.3V LVPECL/HSTL to HSTL 1:9 High-  
Performance Clock Driver with LVTTL  
Clock Select and Enable  
General Description  
The SY89809AL is a high-performance bus clock driver  
with nine differential High-Speed Transceiver Logic (HSTL)  
output pairs. The part is designed for use in low-voltage  
(3.3V/1.8V) applications, which require a large number of  
outputs to drive precisely aligned, ultra-low skew signals to  
their destination. The input is multiplexed from either HSTL  
or Low-Voltage Positive-Emitter-Coupled Logic (LVPECL)  
by the CLK_SEL pin. The Output Enable (OE) is  
synchronous so that the outputs will only be  
enabled/disabled when they are already in the LOW state.  
This avoids any chance of generating a runt clock pulse  
when the device is enabled/disabled as can happen with  
an asynchronous control.  
Precision Edge®  
Features  
3.3V core supply, 1.8V output supply for reduced power  
LVPECL and HSTL inputs  
Nine differential HSTL (low-voltage swing) output pairs  
HSTL outputs drive 50-to-ground with no offset voltage  
750MHz maximum clock frequency  
Low part-to-part skew (100ps typical)  
Low pin-to-pin skew (15ps typical)  
Available in 32-pin TQFP  
The SY89809AL features low pin-to-pin skew (15ps  
typical) and low part-to-part skew (100ps typical). The  
SY89809AL is available in a single space-saving package,  
enabling a lower overall cost solution.  
Applications  
High-performance PCs  
Workstations  
Parallel processor-based systems  
Other high-performance computing  
Communications  
Datasheets and support documentation can be found on  
Micrel’s web site at: www.micrel.com.  
Block Diagram  
Level  
Direction Signal  
HSTL  
Input  
Output  
Input  
Input  
HSTL_CLK, /HSTL_CLK  
HSTL  
Q0 – Q8, /Q0 – /Q8  
LVPECL  
LVCMOS/LVTTL  
LVPECL_CLK, /LVPECL_CLK  
CLK_SEL, OE  
Table 1. Signal Groups  
OE(1) CLK_SEL  
Q0 – Q8  
LOW  
/Q0 – /Q8  
0
0
1
1
0
1
0
1
HIGH  
LOW  
HIGH  
HSTL_CLK  
/HSTL_CLK  
LVPECL_CLK /LVPECL_CLK  
Table 2. Truth Table  
Note:  
1. The OE (output enable) signal is synchronized with the low level of  
the HSTL_CLK and LVPECL_CLK signal.  
Precision Edge is a registered trademark of Micrel, Inc.  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com  
M9999-070110  
July 2010  
hbwhelp@micrel.com or (408) 955-1690  

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