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SY100S815ZG-TR

更新时间： 2024-09-16 20:57:39
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
5页 57K
描述
100S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

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中文翻译

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SY100S815ZG-TR 技术参数

生命周期：Active包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.69系列：100S
输入调节：DIFFERENTIAL MUXJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：10.34 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER功能数量：1
反相输出次数：端子数量：16
实输出次数：8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：0.73 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：2.65 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：ECL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.52 mmBase Number Matches：1

SY100S815ZG-TR 数据手册

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®  
®
SINGLE SUPPLY QUAD  
PECL/TTL-TO-PECL  
Precision Edge  
SY100S815  
FEATURES  
■ Quad PECL version of popular ECLinPS E111  
■ Low skew  
®
Precision Edge  
■ Guaranteed skew spec  
DESCRIPTION  
■ TTL enable input  
The SY100S815 is a low skew 1-to-4 PECL differential  
driver designed for clock distribution in new, high-  
performance PECL systems. It accepts either a PECL  
clock input or a TTL input by using the TTL enable pin TEN.  
When the TTL enable pin is HIGH, the TTL input is enabled  
and the PECL input is disabled. When the enable pin is set  
LOW, the TTL input is disabled and the PECL input is  
enabled.  
■ Selectable TTL or PECL clock input  
■ Single +5V supply  
■ Differential internal design  
■ PECL I/O fully compatible with industry standard  
■ Internal 75kΩ PECL input pull-down resistors  
■ Available in 16-pin SOIC package  
The device is specifically designed and produced for low  
skew. The interconnect scheme and metal layout are  
carefully optimized for minimal gate-to-gate skew within  
the device. Wafer characterization and process control  
ensure consistent distribution of propagation delay from lot  
to lot. Since the S815 shares a common set of “basic”  
processing with the other members of the ECLinPS family,  
wafer characterization at the point of device personalization  
allows for tighter control of parameters, including  
propagation delay.  
To ensure that the skew specification is met, it is  
necessary that both sides of the differential output are  
terminated into 50Ω, even if only one side is being used. In  
most applications, all nine differential pairs will be used  
and, therefore, terminated. In the case where fewer than  
nine pairs are used, it is necessary to terminate at least the  
output pairs on the same package side (i.e. sharing the  
same VCCO as the pair(s) being used on that side) in order  
to maintain minimum skew.  
BLOCK DIAGRAM  
Q0  
Q0  
Q1  
Q1  
Q2  
Q2  
Q3  
Q3  
EIN  
0
EIN  
1
TIN  
TEN  
PIN NAMES  
Pin  
Function  
EIN, EIN  
Differential PECL Input Pair  
TTL Input  
TIN  
TEN  
TTL Input Enable  
Q0, Q0 – Q3, Q3  
Differential PECL Outputs  
PECL VCC (+5.0V)  
PECL Ground (0V)  
VCC  
VEE  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: G  
Amendment: /0  
M9999-032406  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  
12345

中文翻译

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