SY100S834ZGTR

更新时间： 2024-11-06 02:58:39

品牌	Logo	应用领域
麦瑞 - MICREL		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
5页	62K
描述
(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION CHIP

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技术参数
数据手册
替代型号

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SY100S834ZGTR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.65	Is Samacsys：	N
其他特性：	ALSO OPERATES WITH -4.2V TO -5.5V SUPPLY	系列：	100S
输入调节：	DIFFERENTIAL	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4	长度：	9.93 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	湿度敏感等级：	1
功能数量：	1	反相输出次数：
端子数量：	16	实输出次数：	3
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	-4.5 V	Prop。Delay @ Nom-Sup：	1.2 ns
传播延迟（tpd）：	1.2 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.05 ns	座面最大高度：	1.73 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.94 mm	Base Number Matches：	1

SY100S834ZGTR 数据手册

Precision Edge®

SY100S834

Precision Edge

Micrel, Inc.

SY100S834L

(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8)

CLOCK GENERATION CHIP

SY100S834

SY100S834L

FEATURES

■ 3.3V and 5V power supply options

■ 50ps output-to-output skew

Precision Edge

■ Synchronous enable/disable

DESCRIPTION

■ Master Reset for synchronization

■ Internal 75KΩ input pull-down resistors

■ Available in 16-pin SOIC package

The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,

÷4, ÷8) clock generation chip designed explicitly for low

skew clock generation applications. The internal dividers

are synchronous to each other, therefore, the common

output edges are all precisely aligned. The devices can

be driven by either a differential or single-ended ECL or,

if positive power supplies are used, PECL input signal.

In addition, by using the VBB output, a sinusoidal source

can be AC-coupled into the device. If a single-ended

input is to be used, the VBB output should be connected

to the CLK input and bypassed to ground via a 0.01µF

capacitor. The VBB output is designed to act as the

switching reference for the input of the SY100S834/L

under single-ended input conditions. As a result, this pin

can only source/sink up to 0.5mA of current.

The Function Select (FSEL) input is used to determine

what clock generation chip function is. When FSEL input

is LOW, SY100S834/L functions as a divide by 2, by 4

and by 8 clock generation chip. However, if FSEL input

is HIGH, it functions as a divide by 1, by 2 and by 4

clock generation chip. This latter feature will increase

the clock frequency by two folds.

TRUTH TABLE

CLK

Function

Divide

Hold Q0–2

Reset Q0–2

Notes:

Z = LOW-to-HIGH transition

ZZ = HIGH-to-LOW transition

FSEL

Q0 Outputs

Divide by 2

Divide by 1

Q1 Outputs

Divide by 4

Divide by 2

Q2 Outputs

Divide by 8

Divide by 4

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

PIN NAMES

CLK

FSEL

Function

Differential Clock Inputs

Function Select

Synchronous Enable

Master Reset

VBB

Reference Output

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple SY100S834/Ls in a system.

Differential ÷1 or ÷2 Outputs

Differential ÷2 or ÷4 Outputs

Differential ÷4 or ÷8 Outputs

Precision Edge is a registered trademark of Micrel, Inc.

Rev.: G

Amendment:/0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5

中文翻译

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SY100S834ZGTR 替代型号

型号	品牌	替代类型	描述	数据表
SY100S834LZG	MICREL	功能相似	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834ZG	MICREL	功能相似	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834LZC	MICREL	功能相似	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION

与SY100S834ZGTR相关器件

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SY100S838/L	ETC	获取价格	(÷1. ÷2/3) or (÷2. ÷4/6) PECL Clock Generatio
SY100S838_06	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
SY100S838L	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
SY100S838LZC	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
SY100S838LZC	MICROCHIP	获取价格	Low Skew Clock Driver, 100S Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20
SY100S838LZCTR	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
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