Datasheet > SY100S839VZC

SY100S839VZC

更新时间： 2024-11-09 20:53:55

品牌	Logo	应用领域
美国微芯 - MICROCHIP		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
6页	98K
描述
Low Skew Clock Driver, 100S Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20, 0.300 INCH, SOIC-20

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SY100S839VZC 技术参数

是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	SOIC	包装说明：	SOP, SOP20,.4
针数：	20	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.44
Is Samacsys：	N	其他特性：	IT OPERATES VEE=-4.2 TO -5.5V AT ECL MODE
系列：	100S	输入调节：	DIFFERENTIAL
JESD-30 代码：	R-PDSO-G20	长度：	12.83 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	20
实输出次数：	8	最高工作温度：	85 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
最大电源电流（ICC）：	95 mA	传播延迟（tpd）：	0.975 ns
Same Edge Skew-Max（tskwd）：	0.05 ns	座面最大高度：	2.65 mm
最大供电电压 (Vsup)：	3.8 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	ECL	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.52 mm
最小 fmax：	1000 MHz	Base Number Matches：	1

SY100S839VZC 数据手册

NOT RECOMMENDED FOR NEW DESIGNS

Precision Edge^®

÷2/4, ÷4/5/6 CLOCK

GENERATION CHIP

SY100S839V

Micrel, Inc.

Precision Edge

SY100S839V

FEATURES

ꢀ 3.3V and 5V power supply option

ꢀ 50ps output-to-output skew

Precision Edge

ꢀ 50% duty cycle outputs

ꢀ Synchronous enable/disable

ꢀ Master Reset for synchronization

ꢀ Internal 75KΩ input pull-down resistors

ꢀ Available in 20-pin SOIC package

DESCRIPTION

The SY100S839V is a low skew ÷2/4, ÷4/5/6 clock

generation chip designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The device can be driven

by either a differential or single-ended ECL/LVECL or, if

positive power supplies are used, PECL/LVPECL input

signal. In addition, by using the VBB output, a sinusoidal

source can be AC-coupled into the device. If a single-

ended input is to be used, the VBB output should be

connected to the /CLK input and bypassed to ground via

a 0.01µF capacitor. The VBB output is designed to act as

the switching reference for the input of the S839V under

single-ended input conditions. As a result, this pin can

only source/sink up to 0.5mA of current.

The common enable (/EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

Upon start-up, the internal flip-flops will attain a

random state; the master reset (MR) input must be

asserted to ensure synchronization. For systems which

only use one S839V, the MR pin need not be exercised

as the internal divider designs ensures synchronization

between the ÷2/4, and the ÷4/5/6 outputs of a single

device.

Precision Edge is a registered trademark of Micrel, Inc.

Rev.: B

Amendment: /0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5 6

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与SY100S839VZC相关器件

型号	品牌	获取价格	描述	数据表
SY100S839VZCTR	MICREL	获取价格	±2/4, ±4/5/6 CLOCK GENERATION CHIP
SY100S839VZG	MICREL	获取价格	±2/4, ±4/5/6 CLOCK GENERATION CHIP
SY100S839VZGTR	MICREL	获取价格	±2/4, ±4/5/6 CLOCK GENERATION CHIP
SY100S839VZG-TR	MICROCHIP	获取价格	100S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
SY100S863	MICREL	获取价格	8-INPUT PECL DIFFERENTIAL MUX WITH TTL SELECTS
SY100S863_06	MICREL	获取价格	8-INPUT PECL DIFFERENTIAL MUX WITH TTL SELECTS
SY100S863JC	MICREL	获取价格	8-INPUT PECL DIFFERENTIAL MUX WITH TTL SELECTS
SY100S863JCTR	MICREL	获取价格	8-INPUT PECL DIFFERENTIAL MUX WITH TTL SELECTS
SY100S863JZ	MICREL	获取价格	8-INPUT PECL DIFFERENTIAL MUX WITH TTL SELECTS
SY100S863JZTR	MICREL	获取价格	8-INPUT PECL DIFFERENTIAL MUX WITH TTL SELECTS

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