SY100S834ZITR

更新时间： 2024-09-15 22:07:15

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
4页	71K
描述
(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION CHIP

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中文翻译

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数据手册
替代型号

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SY100S834ZITR 数据手册

ClockWorks™

SY100S834

SY100S834L

(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8)

CLOCK GENERATION CHIP

FEATURES

DESCRIPTION

■ 3.3V and 5V power supply options

■ 50ps output-to-output skew

The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,

÷4, ÷8) clock generation chip designed explicitly for low

skew clock generation applications. The internal dividers

are synchronous to each other, therefore, the common

output edges are all precisely aligned. The devices can

be driven by either a differential or single-ended ECL or,

if positive power supplies are used, PECL input signal.

In addition, by using the VBB output, a sinusoidal source

can be AC-coupled into the device. If a single-ended

input is to be used, the VBB output should be connected

to the CLK input and bypassed to ground via a 0.01µF

capacitor. The VBB output is designed to act as the

switching reference for the input of the SY100S834/L

under single-ended input conditions. As a result, this pin

can only source/sink up to 0.5mA of current.

The Function Select (FSEL) input is used to determine

what clock generation chip function is. When FSEL input

is LOW, SY100S834/L functions as a divide by 2, by 4

and by 8 clock generation chip. However, if FSEL input

is HIGH, it functions as a divide by 1, by 2 and by 4

clock generation chip. This latter feature will increase

the clock frequency by two folds.

■ Synchronous enable/disable

■ Master Reset for synchronization

■ Internal 75KΩ input pull-down resistors

■ Available in 16-pin SOIC package

PIN CONFIGURATION/BLOCK DIAGRAM

÷1 or ÷2

SEL

CLK

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

÷2 or ÷4

CLK

VCC

VBB

10 MR

÷4 or ÷8

VEE

SOIC

TOP VIEW

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple SY100S834/Ls in a system.

PIN NAMES

TRUTH TABLE

CLK

FSEL

Function

CLK

Function

Divide

Differential Clock Inputs

Function Select

Hold Q0–2

Synchronous Enable

Master Reset

Reset Q0–2

VBB

NOTES:

Reference Output

Z = LOW-to-HIGH transition

ZZ = HIGH-to-LOW transition

Differential ÷1 or ÷2 Outputs

Differential ÷2 or ÷4 Outputs

Differential ÷4 or ÷8 Outputs

FSEL

Q0 Outputs

Divide by 2

Divide by 1

Q1 Outputs

Divide by 4

Divide by 2

Q2 Outputs

Divide by 8

Divide by 4

Rev.: F

Amendment:/0

IssueDate: September,1999

12 3 4

中文翻译

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SY100S834ZITR 替代型号

型号	品牌	替代类型	描述	数据表
SY100S834LZGTR	MICREL	功能相似	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834ZGTR	MICREL	功能相似	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION

与SY100S834ZITR相关器件

型号	品牌	获取价格	描述	数据表
SY100S838	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
SY100S838/L	ETC	获取价格	(÷1. ÷2/3) or (÷2. ÷4/6) PECL Clock Generatio
SY100S838_06	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
SY100S838L	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
SY100S838LZC	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
SY100S838LZC	MICROCHIP	获取价格	Low Skew Clock Driver, 100S Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20
SY100S838LZCTR	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
SY100S838LZG	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI
SY100S838LZG	MICROCHIP	获取价格	100S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
SY100S838LZGTR	MICREL	获取价格	(±1, ±2/3) OR (±2, ±4/6) CLOCK GENERATION CHI

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