Datasheet > SY100S834_06

SY100S834_06

更新时间： 2024-11-06 05:04:27

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
5页	62K
描述
(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION CHIP

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中文翻译

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数据手册

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SY100S834_06 数据手册

Precision Edge®

SY100S834

Precision Edge

Micrel, Inc.

SY100S834L

(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8)

CLOCK GENERATION CHIP

SY100S834

SY100S834L

FEATURES

■ 3.3V and 5V power supply options

■ 50ps output-to-output skew

Precision Edge

■ Synchronous enable/disable

DESCRIPTION

■ Master Reset for synchronization

■ Internal 75KΩ input pull-down resistors

■ Available in 16-pin SOIC package

The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,

÷4, ÷8) clock generation chip designed explicitly for low

skew clock generation applications. The internal dividers

are synchronous to each other, therefore, the common

output edges are all precisely aligned. The devices can

be driven by either a differential or single-ended ECL or,

if positive power supplies are used, PECL input signal.

In addition, by using the VBB output, a sinusoidal source

can be AC-coupled into the device. If a single-ended

input is to be used, the VBB output should be connected

to the CLK input and bypassed to ground via a 0.01µF

capacitor. The VBB output is designed to act as the

switching reference for the input of the SY100S834/L

under single-ended input conditions. As a result, this pin

can only source/sink up to 0.5mA of current.

The Function Select (FSEL) input is used to determine

what clock generation chip function is. When FSEL input

is LOW, SY100S834/L functions as a divide by 2, by 4

and by 8 clock generation chip. However, if FSEL input

is HIGH, it functions as a divide by 1, by 2 and by 4

clock generation chip. This latter feature will increase

the clock frequency by two folds.

TRUTH TABLE

CLK

Function

Divide

Hold Q0–2

Reset Q0–2

Notes:

Z = LOW-to-HIGH transition

ZZ = HIGH-to-LOW transition

FSEL

Q0 Outputs

Divide by 2

Divide by 1

Q1 Outputs

Divide by 4

Divide by 2

Q2 Outputs

Divide by 8

Divide by 4

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

PIN NAMES

CLK

FSEL

Function

Differential Clock Inputs

Function Select

Synchronous Enable

Master Reset

VBB

Reference Output

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple SY100S834/Ls in a system.

Differential ÷1 or ÷2 Outputs

Differential ÷2 or ÷4 Outputs

Differential ÷4 or ÷8 Outputs

Precision Edge is a registered trademark of Micrel, Inc.

Rev.: G

Amendment:/0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5

中文翻译

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与SY100S834_06相关器件

型号	品牌	获取价格	描述	数据表
SY100S834_09	MICREL	获取价格	(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8) CLOCK GENERATION
SY100S834_11	MICREL	获取价格	(Ã·1, Ã·2, Ã·4) or (Ã·2, Ã·4, Ã·8) Clock Gene
SY100S834L	MICREL	获取价格	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834L	MICROCHIP	获取价格	The SY100S834/L is low skew (÷1, ÷2, ÷4) or (
SY100S834LZC	MICREL	获取价格	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834LZCTR	MICREL	获取价格	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834LZG	MICREL	获取价格	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834LZG	MICROCHIP	获取价格	100S SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100S834LZGTR	MICREL	获取价格	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834LZG-TR	MICROCHIP	获取价格	100S SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

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