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SY100H601JZ

更新时间： 2024-11-06 04:50:11

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	61K
描述
9-BIT ECL-TO-TTL WITH 3-STATE ENABLE

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数据手册

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SY100H601JZ 数据手册

SY10H601

Micrel, Inc.

SY100H601

9-BIT ECL-TO-TTL

SY10H601

SY100H601

WITH 3-STATE ENABLE

DESCRIPTION

FEATURES

■ 9-bit ideal for byte-parity applications

■ 3-state TTL outputs

The SY10/100H601 are 9-bit, dual supply ECL-to-TTL

translators. Devices in the Micrel 9-bit translator series

utilize the 28-lead PLCC for optimal power pinning, signal

flow-through and electrical performance.

The devices feature a 48mA TTL output stage and AC

performance is specified into both a 50pF and 200pF

load capacitance. For the 3-state output disable, both

ECL and TTL control inputs are provided, allowing

maximum design flexibility.

■ Flow-through configuration

■ Extra TTL and ECL power/ground pins to minimize

switching noise

■ ECL and TTL 3-state control inputs

■ 4.8ns max. delay into 50pF, 9.6ns into 200pF (all

outputs switching)

The 10H version is compatible with MECL 10KH ECL

logic levels. The 100H version is compatible with 100K

levels.

■ PNP TTL inputs for low loading

■ Choice of ECL compatibility: MECL 10KH (10Hxxx)

or 100K (100Hxxx)

■ Fully compatible with MC10H/100H601

■ Available in 28-pin PLCC package

PIN NAMES

BLOCK DIAGRAM

Function

TTL Ground (0V)

OEECL

OETTL

GND

VCCE

VCCT

VEE

ECL VCC (0V)

TTL Supply (+5.0V)

ECL Supply (–5.2/–4.5V)

Data Inputs (ECL)

Data Outputs (TTL)

3-State Control (ECL)

3-State Control (TTL)

D0–D8

Q0–Q8

OEECL

OETTL

ECL

TTL

Rev.: E

Amendment: /0

M9999-032906

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4

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