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SY100H607JZ

更新时间： 2024-11-06 04:50:11

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
5页	65K
描述
REGISTERED HEX PECL-TO-TTL

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数据手册
替代型号

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SY100H607JZ 数据手册

SY10H607

Micrel, Inc.

SY100H607

REGISTERED HEX

PECL-TO-TTL

SY10H607

SY100H607

DESCRIPTION

FEATURES

■ Differential PECL data and clock inputs

■ 48mA sink, 15mA source TTL outputs

■ Single +5V power supply

The SY10/100H607 are 6-bit, registered, dual supply

PECL-to-TTL translators. The devices feature differential

PECL inputs for both data and clock. The TTL outputs

feature 48mA sink, 15mA source drive capability for

driving high fanout loads. The asynchronous master reset

control is a PECL level input.

■ Multiple power and ground pins to minimize noise

■ Specified within-device skew

With its differential PECL inputs and TTL outputs, the

H607 device is ideally suited for the receive function of a

HPPI bus-type board-to-board interface application. The

on-chip registers simplify the task of synchronizing the

data between the two boards.

■ VBB output for single-ended use

■ Fully compatible with MC10H/100H607

■ Available in 28-pin PLCC package

The device is available in either ECL standard: the

10H device is compatible with 10K logic levels, while the

100H device is compatible with 100K logic levels.

BLOCK DIAGRAM

PIN NAMES

D0 – D5

Function

True PECL Data Inputs

Inverted PECL Data Inputs

Differential PECL Clock Input

PECL Master Reset Input

TTL Outputs

1 OF 6 BITS

D0 – D5

CLK, CLK

Q0 – Q5

VCCE

CLK

PECL VCC (5.0V)

VCCT

TTL VCC (5.0V)

TGND

EGND

VBB

TTL Ground

PECL Ground

CLK

VBB Reference Output (PECL)

VBB

Rev.: G

Amendment: /0

M9999-032906

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5

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SY100H607JZ 替代型号

型号	品牌	替代类型	描述	数据表
SY100H607JZTR	MICREL	功能相似	REGISTERED HEX PECL-TO-TTL

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