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SY100H603JCTR

更新时间： 2024-09-15 22:34:07

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	75K
描述
9-BIT LATCHED ECL-TO-TTL

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中文翻译

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数据手册

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SY100H603JCTR 数据手册

9-BIT LATCHED

ECL-TO-TTL

SY10H603

SY100H603

DESCRIPTION

FEATURES

■ 9-bit ideal for byte-parity applications

■ 3-state TTL outputs

The SY10/100H603 are 9-bit, dual supply ECL-to-TTL

translators. Devices in the Micrel-Synergy 9-bit translator

series utilize the 28-lead PLCC for optimal power pinning,

signal flow-through and electrical performance.

The devices feature a 48mA TTL output stage and AC

performance is specified into both a 50pF and 200pF

load capacitance. Latching is controlled by Latch Enable

(LEN) and Master Reset (MR) resets the latches. A HIGH

on OEECL sends the outputs into the high impedance

state. All control inputs are ECL level.

■ Flow-through configuration

■ Extra TTL and ECL power/ground pins to minimize

switching noise

■ Dual supply

■ 6.0ns max. delay into 50pF, 12ns into 200pF (all

outputs switching)

■ PNP TTL inputs for low loading

The 10H version is compatible with MECL 10KH ECL

logic levels. The 100H version is compatible with 100K

levels.

■ Choice of ECL compatibility: MECL 10KH (10Hxxx)

or 100K (100Hxxx)

■ Fully compatible with Motorola MC10H/100H603

■ Available in 28-pin PLCC package

PIN CONFIGURATION

BLOCK DIAGRAM

25 24 23 22 21 20 19

OEECL

VCCT

VCCE

TOP VIEW

PLCC

GND

10 11

ECL

TTL

PIN NAMES

GND

Function

TTL Ground (0V)

VCCE

VCCT

ECL VCC (0V)

TTL Supply (+5.0V)

ECL Supply (–5.2/–4.5V)

Data Inputs (ECL)

Data Outputs (TTL)

3-state Control (ECL)

Latch Enable (ECL)

Master Reset (ECL)

VEE

D0–D8

Q0–Q8

OEECL

LEN

Rev.: D

Amendment:/0

Issue Date: April, 1998

12 3 4

中文翻译

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