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SY100H607JCTR PDF预览

SY100H607JCTR

更新时间: 2024-11-23 22:06:47
品牌 Logo 应用领域
麦瑞 - MICREL 转换器电平转换器驱动程序和接口锁存器接口集成电路
页数 文件大小 规格书
4页 77K
描述
REGISTERED HEX PECL-TO-TTL

SY100H607JCTR 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.13Is Samacsys:N
最大延迟:6 ns接口集成电路类型:PECL TO TTL TRANSLATOR
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.48 mm湿度敏感等级:1
位数:6功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出锁存器或寄存器:REGISTER
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Level Translators最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:11.48 mmBase Number Matches:1

SY100H607JCTR 数据手册

 浏览型号SY100H607JCTR的Datasheet PDF文件第2页浏览型号SY100H607JCTR的Datasheet PDF文件第3页浏览型号SY100H607JCTR的Datasheet PDF文件第4页 
REGISTERED HEX  
PECL-TO-TTL  
SY10H607  
SY100H607  
FEATURES  
DESCRIPTION  
Differential PECL data and clock inputs  
48mA sink, 15mA source TTL outputs  
Single +5V power supply  
The SY10/100H607 are 6-bit, registered, dual supply  
PECL-to-TTL translators. The devices feature differential  
PECL inputs for both data and clock. The TTL outputs  
feature 48mA sink, 15mA source drive capability for  
driving high fanout loads. The asynchronous master reset  
control is a PECL level input.  
Multiple power and ground pins to minimize noise  
Specified within-device skew  
With its differential PECL inputs and TTL outputs, the  
H607 device is ideally suited for the receive function of a  
HPPI bus-type board-to-board interface application. The  
on-chip registers simplify the task of synchronizing the  
data between the two boards.  
VBB output for single-ended use  
Fully compatible with Motorola MC10H/100H607  
Available in 28-pin PLCC package  
The device is available in either ECL standard: the  
10H device is compatible with 10K logic levels, while the  
100H device is compatible with 100K logic levels.  
BLOCK DIAGRAM  
PIN CONFIGURATION  
1 OF 6 BITS  
25  
24 23 22 21 20 19  
D
D
n
n
D
Q
Qn  
Q2  
Q1  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
D5  
D5  
Q0  
D4  
TOP VIEW  
PLCC  
TGND  
CLK  
CLK  
VBB  
D4  
CLK  
2
VCCE  
D3  
R
3
4
D3  
5
6
7
8
9
10 11  
CLK  
CLK  
PIN NAMES  
MR  
Pin  
D0 – D5  
D0 – D5  
CLK, CLK  
MR  
Function  
VBB  
True PECL Data Inputs  
Inverted PECL Data Inputs  
Differential PECL Clock Input  
PECL Master Reset Input  
TTL Outputs  
Q0 – Q5  
VCCE  
PECL VCC (5.0V)  
VCCT  
TTL VCC (5.0V)  
TGND  
EGND  
VBB  
TTL Ground  
PECL Ground  
VBB Reference Output (PECL)  
Rev.: F  
Amendment:/1  
1
Issue Date: February, 1998  

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