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SY100H641JZ PDF预览

SY100H641JZ

更新时间: 2024-11-06 20:05:35
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
6页 77K
描述
100H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28

SY100H641JZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LEAD FREE, PLASTIC, LCC-28Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N系列:100H
输入调节:DIFFERENTIALJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:2
功能数量:1反相输出次数:
端子数量:28实输出次数:9
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260传播延迟(tpd):5.8 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.5 ns
座面最大高度:4.57 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11.48 mm最小 fmax:135 MHz
Base Number Matches:1

SY100H641JZ 数据手册

 浏览型号SY100H641JZ的Datasheet PDF文件第2页浏览型号SY100H641JZ的Datasheet PDF文件第3页浏览型号SY100H641JZ的Datasheet PDF文件第4页浏览型号SY100H641JZ的Datasheet PDF文件第5页浏览型号SY100H641JZ的Datasheet PDF文件第6页 
®
1  
1  
SY10H641  
®
Precision Edge  
SINGLE SUPPLY 1:9  
PECL-TO-TTL  
SY100H641  
FEATURES  
Input frequencies up to 135MHz  
®
Precision Edge  
PECL-to-TTL version of popular ECLinPS E111  
Guaranteed low skew specification  
Latched input  
DESCRIPTION  
Differential internal design  
The SY10/100H641 are single supply, low skew  
translating 1:9 clock drivers. Devices in the Micrel H600  
translator series utilize the 28-lead PLCC for optimal  
power pinning, signal flow-through and electrical  
performance.  
The devices feature a 24mA TTL output stage with  
AC performance specified into a 50pF load capacitance.  
A latch is provided on-chip. When LEN is LOW (or left  
open, in which case it is pulled LOW by the internal pull-  
downs), the latch is transparent. A HIGH on the enable  
pin (EN) forces all outputs LOW.  
VBB output VECL for single-ended operation  
Single +5V supply  
Reset/enable  
Extra TTL and ECL power/ground pins  
Choice of ECL compatibility: MECL 10KH (10Hxxx)  
or 100K (100Hxxx)  
Available in 28-pin PLCC package  
The 10H version is compatible with MECL 10KH ECL  
logic levels. The 100H version is compatible with 100K  
levels.  
BLOCK DIAGRAM  
TTL Outputs  
Q0  
PIN NAMES  
Pin  
Function  
TTL Ground (0V)  
Q1  
Q2  
GT  
VT  
TTL VCC (+5.0V)  
VE  
ECL VCC (+5.0V)  
GE  
ECL Ground (0V)  
D, D  
VBB  
Q0 - Q8  
EN  
Signal Input (PECL)  
VBB Reference Output (PECL)  
Signal Outputs (TTL)  
Enable Input (PECL)  
Latch Enable Input (PECL)  
Q3  
PECL Input  
D
D
Q
D
Q4  
Q5  
Q6  
LEN  
VBB  
LEN  
EN  
Q7  
Q8  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: E  
Amendment: /0  
M9999-032906  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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