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SY100H841ZC PDF预览

SY100H841ZC

更新时间: 2024-11-27 19:53:23
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 99K
描述
Low Skew Clock Driver, 100H Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO16, 0.300 INCH, SOIC-16

SY100H841ZC 技术参数

生命周期:Active包装说明:SOP, SOP16,.4
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.4系列:100H
输入调节:DIFFERENTIAL LATCHEDJESD-30 代码:R-PDSO-G16
长度:10.3 mm负载电容(CL):50 pF
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.024 A
功能数量:1反相输出次数:
端子数量:16实输出次数:4
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE最大电源电流(ICC):40 mA
传播延迟(tpd):3.7 nsSame Edge Skew-Max(tskwd):0.3 ns
座面最大高度:2.65 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5 mm最小 fmax:160 MHz
Base Number Matches:1

SY100H841ZC 数据手册

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NOT RECOMMENDED FOR NEW DESIGNS  
®
SINGLE SUPPLY QUAD  
PECL-TO-TTL W/LATCHED  
OUTPUT ENABLE  
PrecisionEdge
SY10H841  
SY100H841  
FEATURES  
Translates positive ECL to TTL (PECL-to-TTL)  
300ps pin-to-pin skew  
®
Precision Edge  
500ps part-to-part skew  
Differential internal design for increased noise  
DESCRIPTION  
immunity and stable threshold inputs  
The SY10/100H841 are single supply, low skew  
translating 1:4 clock drivers.  
VBB reference output  
Single supply  
The devices feature a 24mA TTL output stage, with  
AC performance specified into a 50pF load capacitance.  
A latch is provided on-chip. When LEN is LOW (or left  
open, in which case it is pulled low by the internal pull-  
downs) the latch is transparent. A HIGH on the enable  
pin (EN) forces all outputs LOW.  
As frequencies increase to 40MHz and above, precise  
timing and shaping of clock signals becomes extremely  
important. The H841 solves several clock distribution  
problems such as minimizing skew (300ps), maximizing  
clock fanout (24mA drive), and precise duty cycle control  
through a proprietary differential internal design.  
The 10K version is compatible with 10KH ECL logic  
levels. The 100K version is compatible with 100K levels.  
Enable input  
Latch enable input  
Extra TTL and ECL power/ground pins to reduce  
cross-talk/noise  
High drive capability: 24mA each output  
Fully compatible with industry standard 10K, 100K  
I/O levels  
Available in 16-pin SOIC package  
BLOCK DIAGRAM  
Q
Q
Q
Q
0
1
2
3
PIN NAMES  
Pin  
Function  
TTL Ground (0V)  
GT  
VT  
TTL VCC (+5.0V)  
VE  
ECL VCC (+5.0V)  
GE  
ECL Ground (0V)  
V
BB  
D, D  
VBB  
Q0 - Q3  
EN  
Signal Input (PECL)  
VBB Reference Output (PECL)  
Signal Outputs (TTL)  
Enable Input (PECL)  
Latch Enable Input  
D
D
D Q  
LEN  
EN  
LEN  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: G  
Amendment:/0  
M9999-032906  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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