SY100H606

更新时间： 2024-11-06 04:50:11

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
5页	64K
描述
REGISTERED HEX TTL-TO-PECL

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数据手册

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SY100H606 数据手册

SY10H606

Micrel, Inc.

SY100H606

REGISTERED HEX

TTL-TO-PECL

SY10H606

SY100H606

FEATURES

DESCRIPTION

■ Differential 50Ω ECL outputs

The SY10/100H606 are 6-bit, registered, single supply

TTL-to-PECL translators. The devices feature differential

PECL outputs as well as a choice between either a

differential PECL clock input or a TTL clock input. The

asynchronous master reset control is a PECL level input.

With its differential ECL outputs and TTL inputs, the

H606 device is ideally suited for the transmit function of

a HPPI bus-type board-to-board interface application. The

on-chip registers simplify the task of synchronizing the

data between the two boards.

■ Choice between differential PECL or TTL clock input

■ Single +5V power supply

■ VBB output for single-ended use

■ Multiple power and ground pins to minimize noise

■ Specified within-device skew

■ Fully compatible with MC10H/100H606

■ Available in 28-pin PLCC package

The device is available in either ECL standard: the

10H device is compatible with 10K logic levels, while the

100H device is compatible with 100K logic levels.

PIN NAMES

BLOCK DIAGRAM

D0 – D5

Function

TTL Data Inputs

CLK, CLK

TCLK

Differential PECL Clock Inputs

TTL Clock Input

1 OF 6 BITS

PECL Master Reset Input

True PECL Outputs

Q0 – Q5

VCCE

Inverted PECL Outputs

PECL VCC (5.0V)

CLK

VCCT

TTL VCC (5.0V)

GND

TTL/PECL Ground

VBB

VBB Reference Output (PECL)

CLK

TCLK

VBB

Rev.: E

Amendment: /0

M9999-032906

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5

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