SY100H602

更新时间： 2024-09-16 04:50:11

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	63K
描述
9-BIT LATCHED TTL-TO-ECL

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数据手册

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SY100H602 数据手册

SY10H602

Micrel, Inc.

SY100H602

9-BIT LATCHED

TTL-TO-ECL

SY10H602

SY100H602

DESCRIPTION

FEATURES

■ 9-bit ideal for byte-parity applications

■ Flow-through configuration

The SY10/100H602 are 9-bit, dual supply TTL-to-ECL

translators with latches. Devices in the Micrel 9-bit

translator series utilize the 28-lead PLCC for optimal

power pinning, signal flow-through and electrical

performance.

The H602 features D-type latches. Latching is

controlled by Latch Enable (LEN), while the Master Reset

input resets the latches. A post-latch logic enable is also

provided (ENECL), allowing control of the output state

without destroying latch data. All control inputs are ECL

level.

■ Extra TTL and ECL power/ground pins to minimize

switching noise

■ Dual supply

■ 3.5ns max. D to Q

■ PNP TTL inputs for low loading

■ Choice of ECL compatibility: MECL 10KH (10Hxxx)

or 100K (100Hxxx)

■ Fully compatible with MC10H/100H602

■ Available in 28-pin PLCC package

The 10H version is compatible with MECL 10KH ECL

logic levels. The 100H version is compatible with 100K

levels.

BLOCK DIAGRAM

PIN NAMES

Function

TTL Ground (0V)

ENECL

GND

VCCE

VCCO

VCCT

VEE

D Q

ECL VCC (0V)

ECL VCC (0V) — Outputs

TTL Supply (+5.0V)

ECL Supply (–5.2/–4.5V)

Data Inputs (TTL)

D Q

D0–D8

Q0–Q8

ENECL

LEN

Data Outputs (ECL)

Enable Control (ECL)

Latch Enable (ECL)

Master Reset (ECL)

D Q

TTL

D Q

ECL

D Q

LEN

Rev.: E

Amendment: /0

M9999-032906

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4

中文翻译

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