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SY100H602JZTR PDF预览

SY100H602JZTR

更新时间: 2024-11-06 20:15:59
品牌 Logo 应用领域
美国微芯 - MICROCHIP 接口集成电路锁存器
页数 文件大小 规格书
4页 60K
描述
TTL to ECL Translator, 9 Func, True Output, ECL100K, PQCC28, LEAD FREE, PLASTIC, LCC-28

SY100H602JZTR 技术参数

是否无铅: 不含铅生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCJ,
针数:28Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.27Is Samacsys:N
接口集成电路类型:TTL TO ECL TRANSLATORJESD-30 代码:S-PQCC-J28
长度:11.48 mm标称负供电电压:-4.5 V
位数:1功能数量:9
端子数量:28输出锁存器或寄存器:LATCH
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER座面最大高度:4.57 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:11.48 mm
Base Number Matches:1

SY100H602JZTR 数据手册

 浏览型号SY100H602JZTR的Datasheet PDF文件第2页浏览型号SY100H602JZTR的Datasheet PDF文件第3页浏览型号SY100H602JZTR的Datasheet PDF文件第4页 
2  
2  
9-BIT LATCHED  
TTL-TO-ECL  
SY10H602  
SY100H602  
DESCRIPTION  
FEATURES  
9-bit ideal for byte-parity applications  
Flow-through configuration  
The SY10/100H602 are 9-bit, dual supply TTL-to-ECL  
translators with latches. Devices in the Micrel 9-bit  
translator series utilize the 28-lead PLCC for optimal  
power pinning, signal flow-through and electrical  
performance.  
The H602 features D-type latches. Latching is  
controlled by Latch Enable (LEN), while the Master Reset  
input resets the latches. A post-latch logic enable is also  
provided (ENECL), allowing control of the output state  
without destroying latch data. All control inputs are ECL  
level.  
Extra TTL and ECL power/ground pins to minimize  
switching noise  
Dual supply  
3.5ns max. D to Q  
PNP TTL inputs for low loading  
Choice of ECL compatibility: MECL 10KH (10Hxxx)  
or 100K (100Hxxx)  
Fully compatible with MC10H/100H602  
Available in 28-pin PLCC package  
The 10H version is compatible with MECL 10KH ECL  
logic levels. The 100H version is compatible with 100K  
levels.  
BLOCK DIAGRAM  
PIN NAMES  
Pin  
Function  
TTL Ground (0V)  
ENECL  
GND  
VCCE  
VCCO  
VCCT  
VEE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D Q  
EN  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
ECL VCC (0V)  
ECL VCC (0V) — Outputs  
TTL Supply (+5.0V)  
ECL Supply (–5.2/–4.5V)  
Data Inputs (TTL)  
D Q  
EN  
D Q  
EN  
D0–D8  
Q0–Q8  
ENECL  
LEN  
Data Outputs (ECL)  
Enable Control (ECL)  
Latch Enable (ECL)  
Master Reset (ECL)  
D Q  
EN  
MR  
TTL  
D Q  
EN  
ECL  
D Q  
EN  
D Q  
EN  
D Q  
EN  
D Q  
EN  
LEN  
MR  
Rev.: E  
Amendment: /0  
M9999-032906  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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