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SY100H607JC PDF预览

SY100H607JC

更新时间: 2024-11-09 20:32:47
品牌 Logo 应用领域
美国微芯 - MICROCHIP 接口集成电路锁存器
页数 文件大小 规格书
5页 97K
描述
PECL to TTL Translator, 6 Func, True Output, BIPolar, PQCC28

SY100H607JC 技术参数

生命周期:Active包装说明:QCCJ, LDCC28,.5SQ
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.13
Is Samacsys:N最大延迟:6 ns
输入特性:DIFFERENTIAL接口集成电路类型:PECL TO TTL TRANSLATOR
JESD-30 代码:S-PQCC-J28长度:11.48 mm
位数:6功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出锁存器或寄存器:REGISTER
输出极性:TRUE封装主体材料:PLASTIC
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
座面最大高度:4.57 mm最大压摆率:120 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:11.48 mm
Base Number Matches:1

SY100H607JC 数据手册

 浏览型号SY100H607JC的Datasheet PDF文件第2页浏览型号SY100H607JC的Datasheet PDF文件第3页浏览型号SY100H607JC的Datasheet PDF文件第4页浏览型号SY100H607JC的Datasheet PDF文件第5页 
NOT RECOMMENDED FOR NEW DESIGNS  
7  
7  
REGISTERED HEX  
PECL-TO-TTL  
SY10H607  
SY100H607  
DESCRIPTION  
FEATURES  
Differential PECL data and clock inputs  
48mA sink, 15mA source TTL outputs  
Single +5V power supply  
The SY10/100H607 are 6-bit, registered, dual supply  
PECL-to-TTL translators. The devices feature differential  
PECL inputs for both data and clock. The TTL outputs  
feature 48mA sink, 15mA source drive capability for  
driving high fanout loads. The asynchronous master reset  
control is a PECL level input.  
Multiple power and ground pins to minimize noise  
Specified within-device skew  
With its differential PECL inputs and TTL outputs, the  
H607 device is ideally suited for the receive function of a  
HPPI bus-type board-to-board interface application. The  
on-chip registers simplify the task of synchronizing the  
data between the two boards.  
VBB output for single-ended use  
Fully compatible with MC10H/100H607  
Available in 28-pin PLCC package  
The device is available in either ECL standard: the  
10H device is compatible with 10K logic levels, while the  
100H device is compatible with 100K logic levels.  
BLOCK DIAGRAM  
PIN NAMES  
Pin  
D0 – D5  
Function  
True PECL Data Inputs  
Inverted PECL Data Inputs  
Differential PECL Clock Input  
PECL Master Reset Input  
TTL Outputs  
1 OF 6 BITS  
D0 – D5  
CLK, CLK  
MR  
Dn  
D
Q
Qn  
Dn  
Q0 – Q5  
VCCE  
CLK  
PECL VCC (5.0V)  
VCCT  
TTL VCC (5.0V)  
R
TGND  
EGND  
VBB  
TTL Ground  
PECL Ground  
CLK  
CLK  
VBB Reference Output (PECL)  
MR  
VBB  
Rev.: G  
Amendment: /0  
M9999-032906  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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