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STC5420 PDF预览

STC5420

更新时间: 2024-11-19 21:13:03
品牌 Logo 应用领域
CONNOR-WINFIELD ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
70页 2104K
描述
Clock Recovery Circuit, 1-Func, PQFP100, ROHS COMPLIANT, TQFP-100

STC5420 数据手册

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STC5420  
Synchronous Clock for SETS  
Data sheet  
Description  
Features  
Functional Specification  
The RoHS 6/6 compliant STC5420 is a single chip clock  
synchronization solution for applications in SDH/SETS,  
SONET, and Synchronous Ethernet network elements. The  
device is fully compliant with ITU-T G.813 option 1 and 2,  
G.8262 EEC Opt1 and Opt2 and Telcordia GR1244 and  
GR253.  
- Complies with ITU-T G.813 Opt1/Opt2, G.8262 EEC  
Opt1/Opt2, Telcordia GR1244 and GR253 (Stratum3/4E/  
4/SMC)  
- Two timing generators T0 and T4; T4 may lock to T0’s  
synchronized output  
- Supports Master/Slave and Multiple-Master redundant  
application (T0 timing generator only)  
The STC5420 accepts 12 clock reference inputs and gener-  
ates 10 synchronized clock outputs: CLK1~CLK8, frame  
pulse clock CLK8K at 8kHz, and frame pulse clock CLK2K  
at 2kHz. CLK1~CLK8 may be programmed for wide variety  
of frequencies from 1MHz up to 156.25MHz, in 1kHz steps.  
Reference inputs are individually monitored for activity and  
quality. Reference selection may be automatic, manual, and  
hard-wired manual.  
- Provides programmable compensation for phase delay  
between master and slave unit, in 0.1ns steps  
- Accepts external oscillator at frequency of 10MHz,  
12.8MHz, 19.2MHz,or 20MHz with programming  
- Accepts 12 clock reference inputs  
- Supports frequency auto detection or manually accept-  
able frequency for reference inputs. Each of them is  
monitored for activity and quality  
Two independent timing generators, T0 and T4, may oper-  
ate in the Freerun, Synchronized, Pseudo Holdover, and  
Holdover mode. Each timing generator includes a DSP-  
based PLL. Synchronized mode external timing while fre-  
erun and holdover mode are self-timing. T0 supports Mas-  
ter/Slave and Multiple Master operation for redundant  
design. T4 only supports master operation. DSP-based PLL  
technology removes any external component except the  
oscillator. It provides excellent performance and reliability to  
STC5420.  
- Automatic/manual/hard-wired manual reference select  
- Outputs 10 synchronized clock outputs, including 2  
frame pulse clocks CLK8K and CLK2K  
- 10 clock synthesizers generate frequencies  
- Programmable phase skew in synthesizer level  
- Phase-align or hit-less reference locking/switching  
- Programmable loop bandwidth, from 0.1Hz to 100Hz  
- Supports bus interface: Intel, Motorola, Multiplex, SPI  
- Single 3.3V operation  
The STC5420 is clocked by an external oscillator (TCXO or  
OCXO). Using a well-chosen external oscillator ensures the  
STC5420 meet the required specification and standards.  
- IEEE 1149.1 JTAG boundary scan  
- Available in TQFP100 package  
Synthesizer G1  
Synthesizer G2  
CLK1, LVPECL/LVDS  
CLK2, LVPECL/LVDS  
SRCSW  
Master_Slave  
EX_SYNC  
2
Frame8K  
Frame2K  
Composite  
CLK8K  
CLK2K  
Synth  
F
CLK3  
CLK4  
Synthesizer G3  
Synthesizer G4  
T0 Timing  
Generator  
CLK5  
CLK6  
Synthesizer G5  
Synthesizer G6  
Synthesizer G7  
Ref  
Ref Clk  
12  
10 LVCMOS  
+
Monitor  
CLK7  
CLK8  
2 LVPECL/LVDS  
Synthesizer G8  
Synthesizer GT4  
T4 Timing  
Generator  
TCXO  
OCXO  
µ
P Interface  
Figure 1:Functional Block Diagram  
Page 1 of 70 TM112 Rev: 2.0  
Date: September 28, 2011  
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  

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