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STC5425 PDF预览

STC5425

更新时间: 2024-11-23 19:38:43
品牌 Logo 应用领域
CONNOR-WINFIELD ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
48页 778K
描述
Clock Recovery Circuit, 1-Func, PQFP64, ROHS COMPLIANT, TQFP-64

STC5425 数据手册

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STC5425  
Line Card Clock  
Data sheet  
Description  
Features  
Functional Specification  
- Suitable for SONET, SDH, and Synchronous Ethernet  
applications  
The RoHS 6/6 compliant STC5425 is a single chip  
clock synchronization solution for line card applica-  
tions in SDH, SONET, and Synchronous Ethernet  
network elements.  
- Supports 4 different frequencies of external oscillator  
upon soft-reset: 10MHz, 12.8MHz, 19.2MHz, 20MHz  
- Provides three 2kHz or 8kHz external frame sync input  
- Accepts 5 clock reference inputs  
The STC5425 accepts 5 clock reference inputs, 3  
external frame sync inputs (EX_SYNC1, 2, 3) and  
generates 4 synchronized clock outputs. Synchro-  
nized outputs may be programmed for wide variety of  
frequencies from 1MHz up to 156.25MHz, in 1kHz  
steps. Reference inputs are individually monitored for  
activity and quality. Reference selection may be auto-  
matic, manual, or hard-wired manual.  
- Supports automatically frequency detection or manually  
acceptable frequency. Each reference input is monitored  
for activity and quality  
- Automatic, manual, and hard-wired manual reference  
selection  
- Outputs 4 synchronized clock outputs, including 2 frame  
pulse clocks  
- Frequency translation of input clock to a different local  
line card clock  
The timing generator may operate in the Freerun,  
Synchronized, and Holdover. It includes a DSP-  
based PLL. Synchronized mode is external timing  
while freerun and holdover mode are self-timing.  
DSP-based PLL technology removes any external  
component except the oscillator. It provides excellent  
performance and reliability to STC5425.  
- 3 clock synthesizers generate frequencies  
- Phase-align locking or hit-less reference switching  
- Programmable loop bandwidth, from 13Hz to 100Hz  
- Programmable phase skew in synthesizer level  
- SPI bus interface  
The STC5425 is clocked by an external oscillator,  
either a stable TCXO or XO, as required by applica-  
tion.  
- Single 3.3V operation  
- IEEE 1149.1 JTAG boundary scan  
- Available in TQFP64 package  
SRCSW  
8kHz  
Synth  
F
CLK8K  
CLK2K  
2kHz  
EX_SYNC 1  
EX_SYNC 2  
EX_SYNC 3  
Timing  
Synthesizer G1  
Synthesizer G4  
CLK1, LVPECL/LVDS  
Generator  
CLK2  
Ref  
Monitor  
5
Ref Clk  
3 LVCMOS  
+
2 LVPECL/LVDS/LVCMOS  
TCXO  
XO  
SPI Interface  
Figure 1:Functional Block Diagram  
Page 1 of 48 TM113  
Rev: P1.3  
Date: September 20, 2011  
Preliminary  
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice  

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