Datasheet > STC5428

STC5428

更新时间： 2024-11-19 21:21:03

品牌	Logo	应用领域
CONNOR-WINFIELD		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
66页	1007K
描述
ATM/SONET/SDH Clock Recovery Circuit,

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STC5428 数据手册

STC5428

Synchronous Clock for SETS

DATASHEET

Description

Features

Functional Specification

The RoHS compliant STC5428 is a single chip clock syn-

chronization solution for applications in SDH/SETS,

SONET, and Synchronous Ethernet network elements. The

device is fully compliant with ITU-T G.813 option 1 and 2,

G.8262 EEC option 1 and 2, Telcordia GR1244 and GR253.

- Complies with ITU-T G.813 Opt1/Opt2, G.8262 EEC

Opt1/Opt2, Telcordia GR1244 and GR253 (Stratum3/4E/

4/SMC)

- Two timing generators T0 and T4; T4 may lock to T0’s

synchronized output

- Supports Master/Slave and Multiple-Master redundant

application (T0 timing generator only)

The STC5428 accepts 12 clock reference inputs and gener-

ates 10 synchronized clock outputs: CLK1~CLK8, frame

pulse clock CLK8K at 8kHz, and frame pulse clock CLK2K

at 2kHz. CLK1~CLK8 may be programmed for wide variety

of frequencies from 1MHz up to 156.25MHz, in 1kHz steps.

Reference inputs are individually monitored for activity and

quality. Reference selection may be automatic, manual, and

hard-wired manual.

- Provides programmable compensation for phase delay

between master and slave unit, in 0.1ns steps

- Accepts external oscillator at frequency of 10MHz,

12.8MHz, 19.2MHz,or 20MHz with programming

- Accepts 12 clock reference inputs

- Supports frequency auto detection or manually accept-

able frequency for reference inputs. Each of them is

monitored for activity and quality

Two independent timing generators, T0 and T4, may oper-

ate in the Freerun, Synchronized, Pseudo Holdover, and

Holdover mode. Each timing generator includes a DSP-

based PLL. Synchronized mode is an external timing mode

while freerun and holdover are self-timing modes. T0 sup-

ports master/slave and multiple master operation for redun-

dant design. T4 supports master operation only. DSP-based

PLL technology removes any external component except

the oscillator. It provides excellent performance and reliabil-

ity to STC5428.

- Automatic/manual/hard-wired manual reference select

- Outputs 10 synchronized clock outputs, including 2

frame pulse clocks CLK8K and CLK2K

- 10 clock synthesizers generate frequencies

- Programmable phase skew at synthesizer level

- Phase-align or hit-less reference locking/switching

- Programmable loop bandwidth, from 0.1Hz to 100Hz

- Supports SPI bus interface

The STC5428 is clocked by an external oscillator (TCXO or

OCXO). Using a well-chosen external oscillator ensures the

STC5428 meet the required specifications and standards.

- Single 3.3V operation

- IEEE 1149.1 JTAG boundary scan

- 68-pin QFN package

Synthesizer G₁

Synthesizer G₂

CLK1, LVPECL/LVDS

CLK2, LVPECL/LVDS

SRCSW

Master_Slave

Frame8K

Frame2K

Composite

CLK8K

CLK2K

Synth

CLK3

CLK4

EX_SYNC

Synthesizer G₃

Synthesizer G₄

T0 Timing

Generator

CLK5

CLK6

Synthesizer G₅

Synthesizer G₆

Synthesizer G₇

Synthesizer G₈

Ref

Monitor

Ref Clk

10 LVCMOS

CLK7

CLK8

2 LVPECL/LVDS

T4 Timing

Generator

Synthesizer G_T4

SPI Interface

TCXO

OCXO

Figure 1:Functional Block Diagram

Page 1 of 66

Tm126 Rev:0.2

Date: April 3, 2014

Preliminary

12 3 4 5 6 7...66

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STC5NF20V	STMICROELECTRONICS	获取价格	N-CHANNEL 20V - 0.030ohm - 5A TSSOP8 2.7V-DRI
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STC5NF20V_0710	STMICROELECTRONICS	获取价格	N-channel 20V - 0.030Ω - 5A - TSSOP8 2.7V-dri
STC5NF30V	STMICROELECTRONICS	获取价格	N-CHANNEL 30V - 0.027 OHM - 5A TSSOP8 2.7V-DRIVE STripFET II POWER MOSFET
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