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SSTSD201 PDF预览

SSTSD201

更新时间: 2024-11-08 22:50:07
品牌 Logo 应用领域
CALOGIC /
页数 文件大小 规格书
2页 33K
描述
High-Speed Analog N-Channel Enhancement-Mode DMOS FETS

SSTSD201 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOT-143
包装说明:SOT-143, 4 PIN针数:4
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.90.00.00风险等级:5.84
其他特性:LOW NOISE配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:25 V最大漏极电流 (Abs) (ID):0.05 A
最大漏极电流 (ID):0.05 AFET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):0.3 pF最高频带:ULTRA HIGH FREQUENCY BAND
JESD-30 代码:R-PDSO-G4元件数量:1
端子数量:4工作模式:ENHANCEMENT MODE
最高工作温度:125 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):0.3 W最小功率增益 (Gp):8 dB
认证状态:Not Qualified子类别:FET General Purpose Power
表面贴装:YES端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:AMPLIFIER晶体管元件材料:SILICON
Base Number Matches:1

SSTSD201 数据手册

 浏览型号SSTSD201的Datasheet PDF文件第2页 
High-Speed Analog  
N-Channel Enhancement-Mode  
DMOS FETS  
CORPORATION  
SD200 / SD201 / SD202 / SD203 / SSTSD201 / SSTSD203  
FEATURES  
DESCRIPTION  
High gain . . . . . . . . . . . . . . . . . . . . . 8.0 dB min @ 1 GHz  
Low Noise. . . . . . . . . . . . . . . . . . . . . 5.0 dB max @ 1 GHz  
(SD202, SD203, SSTSD203)  
The SD200 series is manufactured utilizing Calogic’s  
proprietary DMOS design and processing techniques. The  
device is designed to operate well through 1 GHz while  
maintaining excellent frequency response, power gain, and  
low noise. The DMOS structure is an inherently low  
capacitance and very high speed design resulting in a device  
that bridges JFETS and GaAs products in performance  
characteristics.  
Low Interelectrode Capacitances  
APPLICATIONS  
High Gain VHF/UHF Amplifiers  
Oscillators  
Mixers  
ORDERING INFORMATION  
Part  
Package  
Temperature Range  
SD200DC  
SD201DC  
SD202DC  
SD203DC  
SSTSD201  
SSTSD203  
XSD200  
XSD201  
XSD202  
XSD203  
4 Lead TO-52 Package  
4 Lead TO-52 Package  
4 Lead TO-52 Package  
4 Lead TO-52 Package  
-55oC to +125oC  
-55oC to +125oC  
-55oC to +125oC  
-55oC to +125oC  
Surface Mount SOT-143 -55oC to +125oC  
Surface Mount SOT-143 -55oC to +125oC  
Sorted Chips in Carriers -55oC to +125oC  
Sorted Chips in Carriers -55oC to +125oC  
Sorted Chips in Carriers -55oC to +125oC  
Sorted Chips in Carriers -55oC to +125oC  
PIN CONFIGURATION  
SCHEMATIC DIAGRAM  
(2)  
DRAIN  
(4)  
CASE, BODY  
CD10-1 SD201, SD203, zener protected  
CD10-2 SD202, SD204, non-zener  
(3)  
GATE  
CASE, B  
G
S
D
(1)  
SOURCE  
GATE (3)  
BODY INTERNALLY CONNECTED TO CASE.  
DIODE PROTECTION ON SD201/SD203 ONLY.  
DRAIN (2)  
PART MARKINGS (SOT-143)  
P/N  
MARKING  
201  
SSTSD201  
SSTSD203  
BODY (4)  
SOT-143  
203  
SOURCE (1)  

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