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SSM3K324R PDF预览

SSM3K324R

更新时间: 2024-11-01 21:19:55
品牌 Logo 应用领域
东芝 - TOSHIBA 开关光电二极管晶体管
页数 文件大小 规格书
9页 218K
描述
TRANSISTOR SMALL SIGNAL, FET, FET General Purpose Small Signal

SSM3K324R 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SMALL OUTLINE, R-PDSO-F3Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.69
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:30 V
最大漏极电流 (ID):4 A最大漏源导通电阻:0.056 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PDSO-F3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:N-CHANNEL
表面贴装:YES端子形式:FLAT
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

SSM3K324R 数据手册

 浏览型号SSM3K324R的Datasheet PDF文件第2页浏览型号SSM3K324R的Datasheet PDF文件第3页浏览型号SSM3K324R的Datasheet PDF文件第4页浏览型号SSM3K324R的Datasheet PDF文件第5页浏览型号SSM3K324R的Datasheet PDF文件第6页浏览型号SSM3K324R的Datasheet PDF文件第7页 
SSM3K324R  
MOSFETs Silicon N-Channel MOS  
SSM3K324R  
1. Applications  
Power Management Switches  
DC-DC Converters  
2. Features  
(1) 1.8-V gate drive voltage.  
(2) Low drain-source on-resistance  
: RDS(ON) = 56 m(max) (@VGS = 4.5 V)  
RDS(ON) = 72 m(max) (@VGS = 2.5 V)  
RDS(ON) = 109 m(max) (@VGS = 1.8 V)  
3. Packaging and Pin Assignment  
1: Gate  
2: Source  
3: Drain  
SOT-23F  
4. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25 )  
Characteristics  
Symbol  
Rating  
Unit  
V
Drain-source voltage  
Gate-source voltage  
Drain current (DC)  
Drain current (pulsed)  
Power dissipation  
VDSS  
VGSS  
ID  
30  
± 12  
(Note 1)  
(Note 1), (Note 2)  
(Note 3)  
4.0  
A
IDP  
10  
PD  
1
2
W
Power dissipation  
(t 10 s)  
(Note 3)  
PD  
Channel temperature  
Storage temperature  
Tch  
Tstg  
150  
-50 to 150  
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the  
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even  
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum  
ratings.  
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook  
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test  
report and estimated failure rate, etc).  
Note 1: Ensure that the channel temperature does not exceed 150 .  
Note 2: Pulse width (PW) 10 ms, duty 1%  
Note 3: Device mounted on an FR4 board. (25.4 mm × 25.4 mm × 1.6 mm ,Cu pad: 645 mm2)  
2013-01-25  
Rev.1.0  
1

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