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SSM3K104TU(T5LDNSO PDF预览

SSM3K104TU(T5LDNSO

更新时间: 2024-09-29 21:02:19
品牌 Logo 应用领域
东芝 - TOSHIBA 开关光电二极管晶体管
页数 文件大小 规格书
5页 183K
描述
Small Signal Field-Effect Transistor, 3A I(D), 20V, 1-Element, N-Channel, Silicon, Metal-Oxide Semiconductor FET

SSM3K104TU(T5LDNSO 技术参数

生命周期:Obsolete包装说明:SMALL OUTLINE, R-PDSO-F3
Reach Compliance Code:unknown风险等级:5.71
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:20 V
最大漏极电流 (ID):3 A最大漏源导通电阻:0.056 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PDSO-F3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:N-CHANNEL表面贴装:YES
端子形式:FLAT端子位置:DUAL
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

SSM3K104TU(T5LDNSO 数据手册

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SSM3K104TU  
TOSHIBA Field Effect Transistor Silicon N-Channel MOS Type  
SSM3K104TU  
Power Management Switch Applications  
High-Speed Switching Applications  
Unit: mm  
1.8 V drive  
Low ON-resistance:  
R
on  
R
on  
R
on  
= 110 m(max) (@V  
= 1.8 V)  
= 2.5 V)  
= 4.0 V)  
GS  
2.1±0.1  
1.7±0.1  
=
=
74 m(max) (@V  
GS  
GS  
56 m(max) (@V  
Absolute Maximum Ratings (Ta = 25°C)  
1
Characteristics  
Drain-Source voltage  
Symbol  
Rating  
20  
Unit  
V
3
2
V
DS  
Gate-Source voltage  
V
± 12  
V
GSS  
DC  
I
3.0  
D
Drain current  
A
Pulse  
I
6.0  
DP  
P
P
800  
D (Note 1)  
D (Note 2)  
Drain power dissipation  
Channel temperature  
mW  
500  
T
150  
°C  
°C  
ch  
1: Gate  
Storage temperature range  
T
55 to 150  
stg  
2: Source  
3: Drain  
UFM  
Note:  
Using continuously under heavy loads (e.g. the application of  
high temperature/current/voltage and the significant change in  
temperature, etc.) may cause this product to decrease in the  
reliability significantly even if the operating conditions (i.e.  
operating temperature/current/voltage, etc.) are within the  
absolute maximum ratings.  
Please design the appropriate reliability upon reviewing the  
Toshiba Semiconductor Reliability Handbook (“Handling  
Precautions”/“Derating Concept and Methods”) and individual  
reliability data (i.e. reliability test report and estimated failure  
rate, etc).  
JEDEC  
JEITA  
TOSHIBA  
2-2U1A  
Weight: 6.6 mg (typ.)  
Note 1: Mounted on a ceramic board.  
(25.4 mm × 25.4 mm × 0.8 t, Cu Pad: 645 mm2 )  
Note 2: Mounted on an FR4 board.  
(25.4 mm × 25.4 mm × 1.6 t, Cu Pad: 645 mm2 )  
Electrical Characteristics (Ta = 25°C)  
Characteristics  
Symbol  
Test Condition  
Min  
Typ.  
Max  
Unit  
V
I
I
= 1 mA, V  
= 1 mA, V  
= 0  
20  
12  
0.4  
6
1
(BR) DSS  
(BR) DSX  
D
D
GS  
GS  
Drain-Source breakdown voltage  
V
V
= −12 V  
Drain cutoff current  
I
V
V
V
V
= 20 V, V  
= 0  
μA  
μA  
V
DSS  
GSS  
DS  
GS  
DS  
DS  
GS  
Gate leakage current  
Gate threshold voltage  
Forward transfer admittance  
I
= ±12 V, V  
= 0  
±1  
1.0  
56  
74  
110  
DS  
V
= 3 V, I = 1 mA  
th  
D
Y ⏐  
= 3 V, I = 2.0 A  
(Note 3)  
(Note 3)  
(Note 3)  
(Note 3)  
10  
44  
53  
70  
320  
62  
51  
18  
14  
S
fs  
D
I
I
I
= 2.0 A, V  
= 1.0 A, V  
= 0.5 A, V  
= 4.0 V  
= 2.5 V  
= 1.8 V  
D
D
D
GS  
GS  
GS  
Drain-Source ON-resistance  
R
mΩ  
DS (ON)  
Input capacitance  
C
V
V
V
= 10 V, V  
= 10 V, V  
= 10 V, V  
= 0, f = 1 MHz  
= 0, f = 1 MHz  
= 0, f = 1 MHz  
pF  
pF  
pF  
iss  
DS  
DS  
DS  
GS  
GS  
GS  
Output capacitance  
C
oss  
Reverse transfer capacitance  
C
rss  
on  
Turn-on time  
Switching time  
t
t
V
V
= 10 V, I = 2 A,  
DD  
GS  
D
ns  
V
= 0 to 2.5 V, R = 4.7 Ω  
Turn-off time  
G
off  
Drain-Source forward voltage  
Note 3: Pulse test  
V
I
= −3.0 A, V = 0 V  
GS  
(Note 3)  
0.85  
1.2  
DSF  
D
Start of commercial production  
2005-02  
1
2014-03-01  

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