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SSM3J118TU PDF预览

SSM3J118TU

更新时间: 2024-10-28 03:51:11
品牌 Logo 应用领域
东芝 - TOSHIBA 晶体开关小信号场效应晶体管光电二极管
页数 文件大小 规格书
5页 132K
描述
Field-Effect Transistor Silicon P-Channel MOS Type High-Speed Switching Applications

SSM3J118TU 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active包装说明:SMALL OUTLINE, R-PDSO-F3
针数:3Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.29
Is Samacsys:N配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:30 V最大漏极电流 (Abs) (ID):1.4 A
最大漏极电流 (ID):1.4 A最大漏源导通电阻:0.24 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PDSO-F3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
极性/信道类型:P-CHANNEL最大功率耗散 (Abs):0.8 W
认证状态:Not Qualified子类别:Other Transistors
表面贴装:YES端子形式:FLAT
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

SSM3J118TU 数据手册

 浏览型号SSM3J118TU的Datasheet PDF文件第2页浏览型号SSM3J118TU的Datasheet PDF文件第3页浏览型号SSM3J118TU的Datasheet PDF文件第4页浏览型号SSM3J118TU的Datasheet PDF文件第5页 
SSM3J118TU  
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type  
SSM3J118TU  
High-Speed Switching Applications  
4 V drive  
Unit: mm  
Low ON-resistance:  
R
R
= 480 m(max) (@V  
= 240 m(max) (@V  
= 4 V)  
on  
GS  
GS  
2.1±0.1  
1.7±0.1  
= 10 V)  
on  
Absolute Maximum Ratings (Ta = 25°C)  
Characteristic  
Drain–source voltage  
Symbol  
Rating  
Unit  
1
2
V
30  
± 20  
V
V
DS  
3
Gate–source voltage  
V
GSS  
DC  
I
1.4  
D
Drain current  
A
Pulse  
I
2.8  
DP  
P
P
800  
D (Note 1)  
D (Note 2)  
Drain power dissipation  
Channel temperature  
mW  
500  
T
150  
°C  
°C  
ch  
Storage temperature range  
T
55 to 150  
stg  
1: Gate  
2: Source  
3: Drain  
Note:  
Using continuously under heavy loads (e.g. the application of  
high temperature/current/voltage and the significant change in  
temperature, etc.) may cause this product to decrease in the  
reliability significantly even if the operating conditions (i.e.  
operating temperature/current/voltage, etc.) are within the  
absolute maximum ratings.  
Please design the appropriate reliability upon reviewing the  
Toshiba Semiconductor Reliability Handbook (“Handling  
Precautions”/“Derating Concept and Methods”) and individual  
reliability data (i.e. reliability test report and estimated failure  
rate, etc).  
UFM  
JEDEC  
JEITA  
TOSHIBA  
2-2U1A  
Weight: 6.6 mg (typ.)  
Note 1: Mounted on a ceramic board.  
(25.4 mm × 25.4 mm × 0.8 t, Cu Pad: 645 mm2 )  
Note 2: Mounted on an FR4 board.  
(25.4 mm × 25.4 mm × 1.6 t, Cu Pad: 645 mm2 )  
Electrical Characteristics (Ta = 25°C)  
Characteristic  
Symbol  
Test Condition  
Min  
Typ.  
Max  
Unit  
V
I
I
= −1 mA, V  
= −1 mA, V  
= 0  
30  
15  
1  
(BR) DSS  
(BR) DSX  
D
D
GS  
Drain–source breakdown voltage  
V
V
= + 20 V  
GS  
Drain cutoff current  
I
V
V
V
V
= −30 V, V  
= 0  
= 0  
μA  
μA  
V
DSS  
DS  
GS  
DS  
DS  
GS  
DS  
Gate leakage current  
Gate threshold voltage  
Forward transfer admittance  
I
= ±16 V, V  
1.2  
0.8  
±1  
2.6  
GSS  
V
= −5 V, I = −1 mA  
D
th  
Y ⏐  
= −5 V, I =− 0.65 A  
(Note 3)  
1.5  
S
fs  
D
I
I
= −0.65 A, V  
= −10 V  
(Note 3)  
(Note 3)  
180  
360  
137  
240  
480  
D
D
GS  
Drain–source ON-resistance  
R
mΩ  
DS (ON)  
= −0.4 A, V  
= −4 V  
GS  
Input capacitance  
C
V
V
V
= −15 V, V  
= −15 V, V  
= −15 V, V  
= 0, f = 1 MHz  
= 0, f = 1 MHz  
= 0, f = 1 MHz  
pF  
pF  
iss  
DS  
DS  
DS  
GS  
GS  
GS  
Output capacitance  
C
39  
20  
oss  
pF  
ns  
V
Reverse transfer capacitance  
C
rss  
on  
Turn-on time  
Switching time  
t
t
15  
V
V
= −15 V, I = −0.65 A,  
D
DD  
GS  
= 0 to 4 V, R = 10  
G
Turn-off time  
14  
off  
Drain–source forward voltage  
Note 3: Pulse test  
V
I
= 1.4 A, V = 0 V  
GS  
(Note 3)  
0.85  
1.2  
DSF  
D
1
2007-11-01  

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