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SN74LVC74AQDREP PDF预览

SN74LVC74AQDREP

更新时间： 2024-11-18 12:15:07
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
13页 550K
描述
DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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中文翻译

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SN74LVC74AQDREP 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP14,.25针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：1.55系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G14JESD-609代码：e4
长度：8.65 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：100000000 Hz
最大I（ol）：0.024 A湿度敏感等级：1
位数：1功能数量：2
端子数量：14最高工作温度：125 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：5.2 ns
传播延迟（tpd）：6 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.91 mm最小 fmax：100 MHz
Base Number Matches：1

SN74LVC74AQDREP 数据手册

 浏览型号SN74LVC74AQDREP的Datasheet PDF文件第2页浏览型号SN74LVC74AQDREP的Datasheet PDF文件第3页浏览型号SN74LVC74AQDREP的Datasheet PDF文件第4页浏览型号SN74LVC74AQDREP的Datasheet PDF文件第5页浏览型号SN74LVC74AQDREP的Datasheet PDF文件第6页浏览型号SN74LVC74AQDREP的Datasheet PDF文件第7页 
SN74LVC74A-EP  
DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCAS751C–DECEMBER 2003–REVISED SEPTEMBER 2007  
1
FEATURES  
•
Controlled Baseline  
•
•
•
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.2 ns at 3.3 V  
–
One Assembly/Test Site, One Fabrication  
Site  
Typical VOLP (Output Ground Bounce) <0.8 V at  
•
•
Extended Temperature Performance of –40°C  
to 125°C and –55°C to 125°C  
VCC = 3.3 V, TA = 25°C  
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
Enhanced Diminishing Manufacturing Sources  
(DMS) Support  
D OR PW PACKAGE  
(TOP VIEW)  
•
•
•
Enhanced Product-Change Notification  
(1)  
Qualification Pedigree  
1CLR  
1D  
14 VCC  
Operates From 2 V to 3.6 V  
1
2
3
4
5
6
7
13  
12  
11  
10  
9
2CLR  
2D  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
1CLK  
1PRE  
1Q  
2CLK  
2PRE  
2Q  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
1Q  
8
GND  
2Q  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as a translator in  
a mixed 3.3 V/5 V system environment.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
ORDERABLE PART NUMBER  
SN74LVC74AQDREP  
TOP-SIDE MARKING  
LVC74AE  
SOIC – D  
Reel of 2500  
–40°C to 125°C  
TSSOP – PW  
SOIC – D  
Reel of 2000  
Reel of 2500  
Reel of 2000  
SN74LVC74AQPWREP  
SN74LVC74AMDREP  
LVC74AE  
LVC74AM  
LVC74AM  
–55°C to 125°C  
TSSOP – PW  
SN74LVC74AMPWREP  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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中文翻译

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SN74LVC74AQDREP 替代型号

型号 品牌 替代类型 描述 数据表
V62/04669-01XE TI

完全替代

 DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC74AMDREP TI

类似代替

 DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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