SN74LVC74DBR

更新时间： 2024-10-02 13:13:51

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
6页	86K
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SN74LVC74DBR 数据手册

SN74LVC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCAS287B – JANUARY 1993 – REVISED JULY 1995

D, DB, OR PW PACKAGE

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

(TOP VIEW)

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

1CLR

1CLK

1PRE

2CLR

2CLK

2PRE

Latch-Up Performance Exceeds 250 mA

Per JEDEC Standard JESD-17

GND

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

Typical V

> 2 V at V

(Output V

Undershoot)

OHV

= 3.3 V, T = 25°C

Inputs Accept Voltages to 5.5 V

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages

description

This dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V

operation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input may be changed without affecting the levels at the outputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

The SN74LVC74 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

†

↑

†

This configuration is nonstable; that is, it does not

persist when PRE or CLR returns to its inactive

(high) level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6

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与SN74LVC74DBR相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC74DR	TI	获取价格	Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear And Preset 14-SOIC -40 to 85
SN74LVC74PWR	TI	获取价格	8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUT
SN74LVC821A	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821A_08	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADB	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADBLE	TI	获取价格	10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-SSOP -40 to 85
SN74LVC821ADBR	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADBRE4	TI	获取价格	LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
SN74LVC821ADGVR	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC821ADGVRE4	TI	获取价格	10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-TVSOP -40 to 85

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